资源列表
bellman-ford
- bellman-ford的模板，方便大家使用，可以直接粘贴使用-bellman-ford template to facilitate the use of paste can be directly used
huisuo
- 利用回朔思想，是想简单路径查询程序，含注释。-The use of retrospective thought, is like a simple path query process, including the Notes.
zhebancharu
- 折半插入排序相对来说要比冒泡插入排序效率要高，是一种思想。-Binary insertion sort insertion sort, relatively speaking than the bubble speed, is a kind of thinking.
asyn_channel
- asynchronous channel
64bit-shift-register-in-verilog
- Verilog based 64 bit shift register design
NJLT
- 此程序可实现在CAD画面画上N个台阶的楼梯,可缩短建筑施工图绘制时间.-This program can be implemented in the CAD screen painting of N steps stairs, drawing shorten construction time.
diff_cmp-2
- 比较器的理想模型 用Verilog-a写的-ideal model of comparator in Verilog-a
Cancer
- detection cancer with matlab software,I use Multi Layer Perceptron(MLP) to detection.
datetest
- 通过获取localtime，按照一定的格式显示当前的系统时间（windows）-display formatted system time
Condensation1
- UDF for condensation process in ansys (fluent)
daqibianjiec-B
- fluent中udf输入大气边界层效应，包括：速度剖面，湍动能和耗散率-fluent in udf enter the atmospheric boundary layer effects, including: velocity profile, turbulent kinetic energy and dissipation rate
DNSSet
- 获取系统相关信息,写入Mac地址和IP地址-Get SYS infomation