资源列表
adder_4
- 详细介绍了四位加法器的verilog代码，还包括详细的testbench代码。-Details of the four adder verilog code, also includes detailed testbench code.
cao_m
- 计算相空间重构，能够直接输出嵌入维的cao程序，-Can be directly embedded dimension cao program output
median1363
- pku1363,1、题目简介： 给出一个数n，1~n的所有整数会以从小到大的顺序入栈，但出栈顺序不定，同时给出几组出栈的顺序，要求判断给出出栈顺序是否可能。 2、算法实现思想： 首先建立一系列的Stack操作，入push，pop，isEmpty，top，clear等 将要判断的出栈序列存储至一个数组map中。然后从最大的n开始到1进行循环压栈和出栈处理。从出栈序列map[]的尾部开始,进栈,不断寻找最大的出栈,次大的出栈...最后若栈空则为Yes,否则为No -pku136
4_12primenumber
- 输入正整数i和n，由程序负责从i开始找起，连续找出n个素数并显示在屏幕上-Enter a positive integer i, n, the program is responsible From i started looking on, to find n consecutive primes and displayed on screen
MINU
- WINTC写的选择菜单小程序，子程序需要自己编写-failed to translate
Changjiang
- 灰色预测程序，预计长江污水排放量，数学建模有用-Population logistic curve modeling, population forecasting model, mathematical modeling is useful
alu
- 一个简单的算术逻辑运算模块的Verilog代码，可进行加、减、自增、自减，比较大小等运算-alu module
jisuanqi
- 设计一个简单的计算器，能够进行加法、减法、乘法和除法功能(整数和浮点数)。格式是先输入一个数，然后输入运算符号，输入另一个数字，最后输出结果。-Design a simple calculator capable of addition, subtraction, multiplication and division functions (integer and floating-point numbers). The format is to enter a number, then ent
xt_TRACE
- This a module which is used to mark packets for tracing. -This is a module which is used to mark packets for tracing.
readfile
- 实现文件读写功能 可以打开一个txt文件读取该文件信息并向另外一个txt文件写入已经读取的信息-Implementation file to read and write functions can open a TXT file and read the file information to another TXT file is written to have read the information
delay
- 在多径信道的建模中，改步骤实现对各条信道进行延时，最后将所有信道的信号相加-In the multi-path channel modeling, change step to achieve the various channel delay, and finally adding the signals of all channels
LbpDescriptor
- LBP特征描述子提取，用于局部二进制编码,-LBP features, local binary coding