资源列表
Led
- FDWEFSDAFEHWARGVERJHTE(FEVEWEFEWEGREQHGERFGQERGEQR)
FPGA_HW_FOR_FTT
- Chirp信号数字下变频的Matlab和ISE+Modelsim交互仿真-Interactive simulation of Matlab and ISE+Modelsim in Chirp signal digital down converter
diandian_dingcan
- Source code features 1, interface: dot food and beverage online booking website, the interface is beautiful and generous. 2, function: the website front desk and the management background function is complete, and contains the complete source code.
run
- juit4官方源代码 很好好的自学资料-juit4 core code it is very important
classmates
- 简单的同学里程序 仅供参考和交流 还请大家多多指教-a sample classmate program
Geographically_WeightedRegression_The_Analysis
- 针对广义的地理加权回归模型的参考资料和相关操作(Reference data for generalized geographically weighted regression models)
xianshi
- 使用matlab编写的有关于显示图片并且能旋转的相关内容-Written about the use of matlab display pictures and can rotate related content
alarm-clock-V0.1
- 小学期用MFC做的小闹钟，用VC++6.0打开-Small alarm clock, with the primary school period to do with MFC VC++6.0 open
stackPstringPlist
- 全面演示了数据结构-栈的六大应用，进制转换，括号匹配，行编辑，迷宫求解，表达式运算，其中包括线性表的实现与使用，字符串的实现与使用，栈的实现与使用-Comprehensive presentation of the data structure- Stack six applications, binary conversion, bracket matching, line editing, maze solving, arithmetic expressions, including lin
android
- phpCI框架下的网站开发，主要实现文件的上传-phpCI under the framework of website development, file upload
AES-based-on-FPGA-jiemi
- 基于FPGA的AES算法实现，使用verilog语言实现。本模块只包含解密过程，没有加密过程。-Implementation of AES algorithm based on FPGA, using Verilog language. This module contains only the decryption process, no encryption process.
FTOD_SDRAM10.3.18
- FPGA与DSP数据接口转换时序，简单实用的，SDRAM时序读写数据。-FPGA and DSP data interface conversion timing, simple and practical, SDRAM read and write data timing.