资源列表
matlab及simulink通信仿真
- 通信系统仿真基本模块，包括串并转换，等价滤波器，基本数值计算，内涵5个小实验(Communication system simulation basic module, including string and conversion, equivalent filter, basic numerical calculation, five small experiments)
OFDM_Trasnmitter_and_Receiver
- OFDM Trasnmitter and Receiver Matlab Code.
DSSS
- Direct Sequence Spread Spectrum (DSSS)
FM
- This is an FM Matlab Code.
PM
- This is a PM Matlab Code.
短信API接口说明文档
- 联通短信API文档，用于用户对联通短信接口的操作，及基本反馈(Unicom SMS API document, for users to Unicom SMS interface operation, and basic feedback)
Untitled2
- 比较了用软判决和硬判决进行viterbi译码的BER-SNR曲线(Compare the BER-SNR curve of viterbi decoding by using hard decision and soft decision)
联通短消息业务联网协议1.2版（SGIP）
- 联通短消息业务联网协议1.2版（SGIP）联通短消息业务联网协议1.2版（SGIP）(sfoaewpfjew oprkqwpe jioetjm oi[jmopjmp]o3wgjioegjm]qengioqejgm-opjgk-0\egj oig jm]gw]opg ]op)
KEY
- 实现按键消抖级检测，通过检测按键，实现LED灯的亮或灭(To achieve the key jitter level detection, through the detection button, LED lights to achieve brightness or extinction)
UART_TEST
- 通过设置串口的波特率、起始位、检验位等参数，进行FPGA的串口通讯(By setting the baud rate, the starting bit, the test bit and other parameters of the serial port, the serial communication of FPGA is carried out)
random_num_gen
- 通过随机数产生原理进行verilog编程，从而实现FPGA的随机数产生(Through random number generation principle for Verilog programming, so as to achieve the FPGA random number generation)
PLL
- 通过对输入时钟进行锁相环IP核配置，产生所需的时钟信号(By configuring the input clock PLL, the IP core generates the desired clock signal)