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  1. dingshiqizhongduan

    0下载:
  2. 定时器中断试验的程序源码,经试验调试已完全调试通可以使用-Timer interrupt testing procedures, debugging has been fully debugged by the test can be used through
  3. 所属分类:Other Embeded program

    • 发布日期:2017-05-05
    • 文件大小:280.06kb
    • 提供者:杨飞
  1. chuankouIAP

    0下载:
  2. 串口IAP实验,STM32开发板自带程序源码,经调试完全可以跑开发板-Serial IAP experiment, STM32 development board comes with the program source code, the debugger can run development board
  3. 所属分类:Other Embeded program

    • 发布日期:2017-05-16
    • 文件大小:3.58mb
    • 提供者:杨飞
  1. chuangkou-kan-mengou

    0下载:
  2. 窗口看门狗实验的程序源码,STM32开发板自带的程序,经调试完全可以通过-Window Watchdog experimental program source code, STM32 development board comes with the program, the debugger can by
  3. 所属分类:Other Embeded program

    • 发布日期:2017-05-05
    • 文件大小:277.8kb
    • 提供者:杨飞
  1. luyinjishiyan

    0下载:
  2. 录音机实验,STM32自带的程序代码经过调试已经完全通过可以使用-Recorder experiment, STM32 comes after debugging code can be used completely by
  3. 所属分类:Other Embeded program

    • 发布日期:2017-05-09
    • 文件大小:1.64mb
    • 提供者:杨飞
  1. CC2540_spiflash

    0下载:
  2. cc2540的spi文档及例程,CC2540通过SPI读写W25Q系列flash-SPI cc2540 documents and routines, SPI read and write through the W25Q CC2540 series flash
  3. 所属分类:SCM

    • 发布日期:2017-05-05
    • 文件大小:76.17kb
    • 提供者:joneming
  1. equalizer

    0下载:
  2. This the code for the channel equalizer and the test bench for this in the verilog code.-This is the code for the channel equalizer and the test bench for this in the verilog code.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-12
    • 文件大小:1.23kb
    • 提供者:rion
  1. convolution

    0下载:
  2. This the code for the convolutional and the test bench for this in the verilog code.-This is the code for the convolutional and the test bench for this in the verilog code.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-12
    • 文件大小:1023byte
    • 提供者:rion
  1. demapperSharp1(16QAM)

    0下载:
  2. This the code for the demapper in the verilog code.-This is the code for the demapper in the verilog code.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-12
    • 文件大小:777byte
    • 提供者:rion
  1. inter_deleaver

    0下载:
  2. This the code for the interleaver and the deinterleaver in the verilog code.-This is the code for the interleaver and the deinterleaver in the verilog code.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:1.87kb
    • 提供者:rion
  1. mapperSharp1(16QAM)

    0下载:
  2. This the code for the mapper in the verilog code.-This is the code for the mapper in the verilog code.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-12
    • 文件大小:697byte
    • 提供者:rion
  1. Voltage-and-current-control-

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  2. 电压电流控制单片机程序,并显示电压电流,电子设计竞赛-Voltage and current control
  3. 所属分类:Other Embeded program

    • 发布日期:2017-05-05
    • 文件大小:37.08kb
    • 提供者:李四
  1. mt9d112_ddr2

    0下载:
  2. 镁光MT9基于FPGA图像采集模块,该模块可同时采集两路视频信号。其包括完整的时序和接口、ddr2内存数据写入和存储、qsys系统的搭建、FPGA与NIOS II联合设计-Micron MT9 based on FPGA image acquisition module, the module can simultaneously capture two video signals. Including the complete timing and interface, ddr2 memory
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-06-22
    • 文件大小:37.39mb
    • 提供者:
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