资源列表
SCI_UART_SPI_CAN_LIN
- SCI_UART_SPI_CAN_LIN等等串行总线的总体描述，以及各种串行总线性能间的比较-SCI_UART_SPI_CAN_LIN etc. Serial Bus general descr iption, Serial Bus and various performance comparison between the
MP3_design_project(based_atmel_at89c51sdnd1)
- 开发工具:keil7 主要IC：at89c51sdnd1(atmel) 说明：mp3播放器详细设计方案，包括电路原理图，物料，源码，下载工具，开发文档，芯片datasheet等。 用途：单芯片mp3的设计实现。-Tools : keil7 major IC : at89c51sdnd1 (atmel) Note : mp3 players detailed design programs, including the circuit diagram, the materials, s
usb_keyboard_design_project(based_ti_tusb2136)
- 开发工具：iar for c51 主要IC：tusb2136(ti)(8052内核) 主要应用：PC外接usb键盘，智能手机/PDA外接usb键盘 备注：使用keil开发工具编译时需要将地址分配固定，对照firmware/release/list下map文件修改源码-Tools : iar for major decoder IC : tusb2136 (ti) (8052 kernel) main applications : PC external usb keyboard, s
USB_PCsdgfdg
- USB大量数据收发PC软件，用VC++开发工具-massive data transceiver USB PC software, development tools with VC
DSP642netCode
- 这个程序是用于数字信号处理dsp 642的物理层通讯的程序。-This procedure is used for digital signal processing dsp 642 of the physical layer communications procedures.
embedwamgjun2
- 将中断向量调整到0x33ffff00地址。 我的理解是中断向量仍然是0x0，只是通过一种转换将这个向量表又复制到0x33ffff00地址了。但是当中断来临的时候，CPU仍然首先指向0x0地址所在的向量表，然后通过这个向量表转向0x33ffff00所在的向量表。-will interrupt vectors 0x33ffff00 adjusted to address. My understanding is interrupted vector is still 0 x0, only thr
cf5_0
- NIOS的CF卡应用,包括了软件和硬件,支持多个系列的PFGA-NIOS the CF card applications, including the hardware and software, to support a number of series PFGA
P18channelLED
- P1口八路LED的驱动程序，汇编语言的源程序-P1 mouth of the Eighth Route Army LED driver, the assembly language source code
ds18b20-asm
- ds18b20-asm.rar，温度传感器ds1820的汇编语言源程序-ds18b20 - asm.rar, temperature sensor ds1820 the assembly language source
c-i2cchengxu
- i2c的c语言程序,包括读写一个字节,读写n个字节的子程序-i2c the c language program, including a byte read and write, read and write n bytes of subroutines! !
16bit_booth_multiplier_STG
- verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-mo
dirital_clock_7
- verilog实现电子时钟模块，输入60Hz时钟信号和复位，输出时分秒，共6位，每位7段输出用于驱动-verilog electronic clock module, 60Hz input clock signal and reset, Minutes exportation, a total of six, each of the seven drivers for output