资源列表
vhdlcodes10
- FPGA/CPLD集成开发环境ise的使用详解 示例代码10-FPGA/CPLD integrated development environment IDE ise the example code 10
vhdlcodes11
- FPGA/CPLD集成开发环境ise的使用详解 示例代码-FPGA/CPLD integrated development environment IDE ise the example code
vhdlcodes9
- FPGA/CPLD集成开发环境ise的使用详解 示例代码9-FPGA/CPLD Integrated Development Environment ise Comments on the use of code examples 9
vhdlthreelinespi
- ＳＰＩ总线与ＣＰＬＤ之间的通信程序，可实现ＳＰＩ串行输入，通过移位寄存器后并行输出-SPI bus and the CPLD communication between these procedures is to realize SPI serial input, through the shift register parallel output after
VHDL_cpld
- 用CPLD做了个FPGA的FPP下载时序，验证过。-done with CPLD- FPGA FPP download timetables tested.
video
- 一个可以在arm板2440上运行的摄像头采集服务端程序-An arm board in 2440 running on the camera capture server program
VideoCode
- 摄像头处理VC代码,可基于此，对摄像头的功能进行补充、融汇。-VC Video Code
video_software
- use of NIOS PIO to simulate I2C bus,to initial TVP5150-use of NIOS PIO to simulate I2C bus, to initial TVP5150
vidio
- 基于s3c2410的摄像头应用程序，已经经过测试-Based on s3c2410 camera application has been tested
viic
- I2C通讯IO口模拟程序 ,只有在SCL线的时钟信号是低电平时才能改变-I2C communication port IO simulation program, only in the SCL line is low when the clock signal can be changed
viterbi
- 一种基于FPGA的Viterbi译码器一种基于FPGA的Viterbi译码器-FPGA-based Viterbi decoder FPGA-based Viterbi decoder
vivi_for_linux2.6.11.1
- vivi_for_linux2.6.11.1编程日志-vivi_for_linux2.6.11.1