资源列表
16bit_booth_multiplier_STG
- verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-mo
dirital_clock_7
- verilog实现电子时钟模块，输入60Hz时钟信号和复位，输出时分秒，共6位，每位7段输出用于驱动-verilog electronic clock module, 60Hz input clock signal and reset, Minutes exportation, a total of six, each of the seven drivers for output
dff_UDP
- verilog实现，UDP描述带有异步复位的正边沿触发D触发器，test测试通过-verilog achieve, UDP asynchronous reset with a descr iption of the fringe is triggered D flip-flop, test test pass
fifo_datapath
- verilog实现，串转并通过fifo再并转串，可以满足输入速率自由输出的一半时，输出仍可持续发送-verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
proteuscode
- proteus 实例这是结合c51编程的例子-proteus examples of this is combined decoder programming examples
keyboardwjf
- this file is for keil keyboard
LCDWJFSANHE
- this file is for keil LCD
Motor2006
- this file is for keil motor-this file is for motor keil
dds_with_lcd1111
- 使用keil C51编译的DDS的LED显示源码-keil C51 compiler to use the DDS source LED Display
ddsquartus
- 使用QUARTUS 2编译的DDS的源码-QUARTUS use two compiled the DDS source
ddsled1234
- 使用keil C51编译的计时器的LED显示源码-use keil C51 compiler of the LED timer FOSS
modbusProgrammer
- modbus协议栈，供大家参考！ 供大家参考！-modbus connection protocol stack, for your reference! For your reference!