资源列表
22
- 使用VHDL实现16进制的计数器的算法程序-Use VHDL to achieve 16 of the counter-band algorithm procedure
SRDFF
- Zip file contains the shiftregister code using verilog HDL
key-dejitter
- 按键去抖模块，避免按键抖动引起的系统误操作。FPGA时钟频率25.000MHZ-Key de-jittering module to avoid system misoperation caused by key-jitter. FPGA clock frequency 25.000MHZ
5renduoshuVHDL
- 5人多数表决VHDL源代码，数码管可以显示倒计时时间和通过的人数-5 Most of the voting machine
VHDL1
- 4位并行加法器，a3,a2,a1,a0,b3,b2,b1,b0,cin为输入，cout,s3,s2,s1,s0为输出-4-bit parallel adder, a3, a2, a1, a0, b3, b2, b1, b0, cin as the input, cout, s3, s2, s1, s0 as the output
subtractor4
- Verilog half subtractor module and tests build with made with gates built with expression modules.
myCLK
- 24Mhz的频率分成2Mhz的频率。 再由一个I/O口输出。-The frequency of 24Mhz into2Mhz frequency，Again by an I/O port output.
parity_check
- Parity checing program in verilog
20120924-1647
- 上位机，简单的从仪器接受程序原始内容，可供测试串口-Epistatic machine, simple from instrument accept program original content, available for testing serial port
c51
- 51数字钟带各种扩展年，月，日等并且可预置。用汇编语言写的-51 digital clock with extended assembly language
RFtest
- NRF24L01 RF测试，该程序为一个载波程序。-NRF24L01 RF testing, the program is a carrier program.
soma_loka
- Sum make in vhdl code