资源列表
DEF
- 一个简单的始终触发器的代码 另外包括测试验证程序和输入码数据
count
- 用VHDL实现一个四位十进制计数器来进行计数，并且仿真通过-To use VHDL to achieve a 4 decimal counter to count, and the simulation through the
ring
- Ring register[1 from 8] which seven speeds. The result is presented on 8 LEDs. After every cycle, speed grows. The process starts again after last 8 cycle.
clk_div
- 一个时钟分频模块,in verilog hdl-clock division module in verilog hdl
lcd
- FPGA嵌入式开发中的NIOSii的LCD1602控制程序。-FPGA NIOSii LCD1602
APU1
- 该程序主要实现迭代加法，实现128次迭代加法-The procedure to achieve iterative addition, to achieve the addition of 128 iterations
MA_HOA_MANCHESTER
- MANCHESTER ENCODING IN VHDL
7121
- SAA7121初始化文件,用于视频图像输出.-SAA7121 initialization files for video output.
Fading2
- Arduino Fadding sample scr ipt
qudongdianji
- 很实用的驱动电机的程序，用于单片机开发,电机驱动用，内有注释，容易理解-a little code of driving motor
f100Hz0.2
- 51单片机100Hz发生器，帮网友编写的-51 Single- Chip Microcomputer 100Hz generator
juzhengjianpan
- 51单片机的矩阵键盘程序，仅供初学者，参考-51 SCM matrix keyboard program, for beginners, reference