资源列表
VerilogHDL-V3.0
- 这是一本讲述verilogHDL的书籍，通俗易学，名字是《VerilogHDL那些事儿》-This is a book about verilogHDL, popular easy to learn, the name is " VerilogHDL that thing"
algorithms
- 关于很多实用算法的描述，例如递归、贪心算法-About the descr iption of a lot of practical algorithms, such as recursive, greedy algorithm and so on
GM8136_AUDIO_LIVESOUND
- GM8136_AUDIO_LIVESOUND包含了GM8136/S平台下声频驱动的例程，给出了所有需要的头文件、驱动程序等。(GM8136_AUDIO_LIVESOUND includes the sample of audio livesound that based on GM8136, besides all of head files and drivers files were included.)
ST20_Toolset_R181
- ST20 Embedded Toolset Version R1.8.1 - STB development platform
Hi3518E-C00
- hi3518e相关资料，含datasheet，api等文档，-hi3518e document，include datasheet，api and so on
ES
- 讲解ARM的PPT课件,和实验箱ARM2410的用法及实验内容-ARM on the PPT courseware, and experimental use of ARM2410 me and experimental content
51
- 51开发板的全套资料，包括PCB文件，原理图-51 development board, a full set of data, including PCB files, schematics
RT-Thread-0.3.1-touchuan
- STM32基于RT-THREAD的串口网络口双向透传代码-STM32-based RT-THREAD bidirectional serial port passthrough network code
LUdecompose
- 基于verilog的LU分解,本文件包括详细的程序代码，运行文件，以及详细的文档-LU decompose based on verilog
pinlvji
- 用4位十进制计数器对用户输入时钟信号进行计数，计数间隔为1秒钟。计数满1秒钟后将计数值（即频率值）所存到4位寄存器中显示，并将计数器清0，在进行下一次计数。 频率计由三种模块组成：testctl为控制模块，由1Hz其准产生rst_cnt,load,cnt_en信号；cnt10为带清0及计数允许的十进制计数器；reg4b为四位寄存器。 -With four decimal counter input clock signal to the user to count, count one
STM32F407——TIM3正交编码器
- 单片机应用中，比较实用的C语言实例，编码器正交编码(SCM application, a more practical example of C language)
LCDCode
- 用51单片机控制的17寸液晶显示器源程序-51 MCU control with 17-inch LCD monitor source code