资源列表
Div20PLL
- 使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享-PLL using VHDL, VHDL is learning a good example, sharing with the public
phase
- 实现两路数字信号的鉴相功能，最后通过静态LED显示出来，该程序通过硬件的测试
jiaotongdeng
- TIDSP2407交通灯程序，希望对大家有用
WatchDog
- 对与单片机常用的功能看门狗，本程序用vhdl硬件语言实现次功能。
FPGA读写控制sram
- 拨码开关控制读写，按键控制地址加，读出数据由数码管显示，直观展现了程序是否正确。
fifo
- 此程序为存储器常用的FIFO（先入先出），程序中没有指明位宽，这样更适合于初学者进行套用-This process commonly used for the memory FIFO (FIFO), the procedure is not specified bit, so more suitable for beginners to apply
AUDIO
- 在TMS320C5509开发板上使用的语言录放程序，程序没有问题-TMS320C5509 development board in the language used in playback program, the program is no problem
2
- 图像分割，将运动图像从背景图像中提取出来。-Image segmentation, the moving image extracted from the background image.
dsp
- 设计了一个低通巴特沃斯滤波器，在其通带边缘 1kHz处的增益为3dB，3kHz处的阻带衰减为 30dB，采样频率 10kHz。 -A low-pass Butterworth filter 3dB gain of of its passband edge 1kHz at 3kHz at the stop-band attenuation 30dB, the sampling frequency is 10kHz.
EUART
- EUSART pic implementation XC8 for pic18f24j10
adder4
- This example illustrates the use of the For Generate statement to construct a ripple-carry adder a full adder function. It also shows how to use a package -This example illustrates the use of the For Generate statement to construct a ripple-carry add
vxworks_myMsq
- 在Vxworks下实现消息队列，满足基本的C/S模型，望大家给出指导意见！非常感谢-Achieved in Vxworks message queue, to meet the basic C/S model, we hope to give guidance! thank you very much