资源列表
squareroot.rar
- vhdl源代码,可以开16比特的平方根，算法简单，速度快,this is a vhdl code for square root
Audio_In_Deserializer
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
vhdl-dianziwannianli
- 基于FPGA的电子万年历，此电子万年历系统主要有8个模块分别设计1. 主控制模块 maincontrol 2. 时间及其设置模块 timepiece_main 3. 时间显示动态位选模块 time_disp_select 4. 显示模块 disp_data_mux 5. 秒表模块 stopwatch 6. 日期显示与设置模块 date_main 7. 闹钟模块 alarmclock 8. 分频模块 fdiv -FPGA-based electronic calen
0308
- 两个按钮控制步进电机正反转和蜂鸣器报警-2 Buttons to control the stepper motor reversing
VIRTEX2-ISE-VHDL
- XILINX virtex5 板子上做演化硬件时ISE 12.1中的硬件构架语言描述-XILINX virtex5 VHDL
DS12C887
- 这是一个电子钟程序，已经通过本人测试通过-this is a clock program ,it has been tested well! I am very happy that it is helpful to you!!
DIWEN(donghua-)
- 迪文屏驱动，含有动画控制的函数.颜色控制等等的函数-diwen screen,dong hua
New-folder
- different method to implement decoder and on for detectorn
51_music
- 单片机开发，用汇编语言编写程序，制作兰花草和生日快乐歌-MCU development, written in assembly language program, making the orchid grass and happy birthday
DSP28_Ev
- 初始化EVA或者EVB，本例中EVA和EVB均产生占空比为40 PWM波形，EVA下面的 定时器均工作于连续增模式，而EVB下面的定时器均工作于连续增/减模式，各 个全比较单元的死区时间为4.27us-Air ratio of 40 PWM waveform, EVA following timers are operating in a continuous growth mode, and EVB following timers are working in a continuous u
fir25
- 用VDHL写的25阶对称FIR滤波器，在塞克隆3FPGA下验证没有问题（AD采样时钟50Mhz，这个对硬件设计有点要求），里面调用官方乘法器API，要节省资源可以采用CSD编码转换乘法器，可以减少一半以上的资源-VDHL written by a 25th order symmetric FIR filter in Seke Long 3FPGA under verify that no problem (AD sampling clock 50Mhz, this design is a bit
chaoshengboceju
- 基于c51的超声波避障程序 超声波避障，精确到毫米 -c51-based ultrasonic obstacle avoidance procedures