资源列表
spiking
- 脉冲反褶积的实现，是一个比较经典的程序哦
107215824washingmachine
- 通过不同的二极管亮，表示洗衣机的不同状态。如正转、反转、洗条、干衣。按下P3_3时，会停止
rec
- 基于vhdl编写的FPGA与PC串行通信的接收信号解码程序，调试已通过。-Vhdl prepared based on FPGA and PC serial communication received signal decoding process, debugging has been passed.
coder_counter
- 增量式光电编码器计数器的FPGA实现程序,verilog3段式FSM,异步加载.-Incremental Optical Encoder counter program FPGA implementation, verilog3 struts FSM, asynchronous load.
CIC_DEC_3
- CIC抽取滤波器设计，CIC滤波器采用5阶3倍抽取。-CIC decimation filter design, CIC filter order 3 times 5 samples.
CIC_DEC_6
- CIC抽取滤波器设计，CIC滤波器采用5阶6倍抽取。-CIC decimation filter design, CIC filter stage 6 times 5 samples.
traffic-light
- 使用verilog实现的简单交通灯控制程序，只是实现的红绿黄灯定时。-traffic light control circuit。however,just including red,green,yellow light
counter
- 实现可控计数器，在用户的控制下，可以实现起点和终点的计数设置-used to count by the user controlling
AT24CX
- AT24C01-AT24C16IIC总线功能模块-AT24C01-AT24C16IIC bus functional modules
FM24C16A_FM24CL16
- FM24C16A 存储芯片 读写程序（单片机通用）-The storage chips read and write procedures in FM24C16A (SCM generic)
Add_Sub_4_Bit
- 这个是vhdl中很简单并且很基础的adder减法编码 主要是为以后的学习ram编码做准备 其中包括fulladder和halfadder-This is a very simple and very vhdl based adder coding is mainly for future learning ram preparation including fulladder coding and halfadder
IIC
- Verilog IIC程序，RAM接口，方便调试，一主多从-Verilog IIC program, RAM interface, easy to debug, and more a master