资源列表
crc.c
- CRC source code for linux environment. CRC for 16 bytes packet. Useful for checking crc of tinyos uart packet.
DDS
- 同时用verilog 语言编写dds原代码用于生成正余弦波，并在FPGA平台进行验证-described dds direct digital frequency synthesis of the basic tenets addition to the use of verilog prepared dds source used to produce sine, and FPGA development platform for verification
USB_API
- USB 文件管理 MCU API 库的连接对象-USB file management MCU API database connection object
vlsiram
- VHDL RAM 16 * 8 source code FPGA
gcd
- 求最大公约数的vhdl 源代码 gcd-gcd
dpll
- dpll is used to lock the data
clk
- 这是一个数字秒表的设计。几时周期为0.01s-1h。带有计数器的清零端，还有一个秒表的计时起止控制开关，最后计时信息显示在数码管上。-This is a digital stopwatch design. When a period of 0.01s-1h. Cleared with the end of the counter, and a stopwatch start and end time-control switch, the last time the information di
PWM
- PWMc语言代码，产生PWM波形，用于各种产品以及测试-PWMc language code to generate PWM waveforms for a variety of products and test
autosell_newspaper
- 這是FPGA自動販賣機的功能,名字為autosell_newspaper.rar,其中使用了有限狀態機。-FPGA vending machines function, the name of the autosell_newspaper.rar, which uses the finite state machine.
ACCUM
- accumulator for direct digital synthesis
cun
- 一个四个地址的四位寄存器，实现存储、读取功能，并在数码管上显示数据的地址-A four addresses four registers for storage, read function, and displays the address of the data on the digital
dds
- 采用硬件描述语言verilog进行DDS变换的实现的代码-Using hardware descr iption languages Verilog implementation of DDS converter code