资源列表
UP3_CLOCK2
- UP3开发板上的时钟控制源代码文件，VHDl编写-degrading development control board clock source documents, prepared VHDl
DSP_EMIF_if
- fpga开发的程序，内容都不错，主要是top_test
Electronic-Design-Automation
- 用vhdl语句描述4位等值比较器，4选1多路选择器，8位奇偶校验电路功能-VHDL language used to describe the equivalent four comparators, 4 election more than one MUX, 8-bit parity circuit functions
lcd
- 用sopc技术实现对128*64的lcd液晶显示。这里是它的程序。 -Sopc technology used for implementation of 128* 64 LCD lcd. Here is the procedure.
OscilloscopePrototype
- A prototype of Digital Oscilloscope
crc8_4
- crc8代码 数据位宽为4 ，用verilog编的码-crc8 datawidth 4 verilog
key
- 中断功能读取键盘,根据键盘值,将对应的led灯点亮-Read the keyboard interrupt function, according to the keyboard value, the corresponding led lights lit
SONGYFQ
- 用VHDL设计的电路，输出接到喇叭可播放乐曲“一分钱”。适合做课程设计。-Circuit design with VHDL, output to speakers can play music, " a penny." Suitable curriculum design.
key
- cpld的按键数码管显示程序 用VHDL编程-cpld key digital display program
FFT-Algorithm-with-the-DSP
- 基于快速傅利叶算法的DSP快速运算,最基础算法工具-Fast Fourier-based DSP algorithm for fast computing, the most basic algorithm tool
16QAM-demapping
- 16QAM的解映射模块和测试模块，主要用的是Nbit的硬性判断法进行解码-16QAM demapping module and test module, please refer to, thank you guidance
CORDIC
- pipelined CORDIC in structural model that contains 16 stages