资源列表
fet140_tb_09
- MSP-FET430P140 Demo - Timer_B, PWM TB1-2, Up/Down Mode, DCO SMCLK-MSP-FET430P140 Demo-Timer_B, PWM TB1-2. Up / Down Mode, the making of SMCLK
TimeOut_C
- SmartARM2200基础实验扩展实验定时器实验-SmartARM2200-based expansion experiment experimental experiments timer
LCD1602
- 16*2字符型液晶屏驱动程序 IO方式，适用于所有51内核的单片机 /************************************** 16x2 Alphanumeric LCD Drivers Author: Peng Jin Biao Email: pengjinbiao@163.com Date: 2007-9-1 Environment: Keil C51 uV2 MCU: 8051 LCD Model: RT1602C Note
sign_by_unsign_multiplication
- sign by unsign and sign by sign multiplication in verilog
full_add
- 全加器，可移植性很强，只需要变换一下里面的数字就能得到任意的全加器！-The counter, portability is very strong, only need to a change in the inside of the digital can get any counter!!!!!
rtl
- led and 7segment with verilog
sram_vhdl
- 基于vhdl的sram读写访问程序，经过前后仿真及板上实际测试-failed to translate
CM_WADDR
- Complex multiplier with twiddle factor
ZIDONGDIANTIKONGZHI
- 三层的电梯控制,具备显示，加速，以及开关门的延时等操作-Three elevator control, including a display, acceleration, and an operation switch gate delay and other
VHDL-8bitFIFO
- FIFO的宽度：也就是英文资料里常看到的THE WIDTH，它只的是FIFO一次读写操作的数据位，就像MCU有8位和16位，ARM 32位等等，本程序实现8位的FIFO功能,三位格雷码可表示8位的深度。-THE WIDTH of THE FIFO: namely information in English often see THE WIDTH, it is only a FIFO data read and write operations, as has 8 bit or 16 bit M
H bridge CPLD driver
- Verilog H bridge driver with a Enable control
trd106s
- CPLD H bridge driver