资源列表
AD&DAConverters
- ADDA转换的经典源代码（A/D & D/A Converters ）-ADDA conversion of the classic source (A / D D / A Converters)
erfenpindevhdlyuveriloghdl
- 这是关于2分频的vhdl实现和verilog hdl实现，都已经仿真验证了其正确性，大家可以对比参考。
dff
- 用vhdl编写的D触发器，锁存器等，不需帐号就可自由下载此源码-VHDL prepared using D flip-flops, latches and so on, no account can be a free download this source
shifter_left_8_8_4
- barrel shifter.实现循环左移的功能，8个输入，8个输出。每个输入或者输出是4位-barrel shifter. 8 inputs,8 outputs. And every input or output has 4bits.
kb_code
- keyboard interfacing
D_VHDL
- FPGA实现的触发器，VHDL描述，等等,可供参考-FPGA implementation of the trigger
motor_DC
- it is a dc motor controller for avr mico controllers.
ADC0809-digital-voltage-meter
- ADC0809简易数字电压表数码管显示c程序-ADC0809 digital voltage meter.
PWMInit
- 飞思卡尔单片机pwm初始化 适用于智能车的舵机和电机驱动 -The Freescale microcontroller pwm initialization for smart servos and motor drive
Tested-Home-Security
- c code for home security system.
u_channel_correction
- 基于FPGA的通道不一致性校正的verilog代码-FPGA-based channel inconsistency correction verilog code
gscoutpur
- DSP PROGRAM FOR GENERALIZED SIDE LOBE CANCELLER IN MATLAB