资源列表
sram读模块基于FPGA的实现
- sram读模块基于FPGA的实现 verilog源代码,sram
CORDIC_design_verilog_digital_computer
- CORDIC数字计算机verilog设计.rar-CORDIC design verilog digital computer. Rar
LCD_stopwatch
- It is stopwatch whereby it display on the LCD.
out_50hz
- 输入频率,用CPLD驱动8位DA,产生正玄信号-用CPLD驱动8位DA,产生正玄信号
time
- 该功能主要是利用定时器来进行计时，基于51单片机。-This feature is mainly used to carry out time timer, based on 51 microcontroller.
RS422_receiver
- UART--异步串行通讯 接收逻辑 （Verilog）16倍时钟接收-verilog--A UART Receiver 16 clock
pointer
- visual dsp++ pointer coding.
BLATC
- 2位垂直极化空时编码以及与其相关的串并转换-Verilog ，Blatc ，Serial to parallel 2bit，Parallel to serial 2bit
DIO-for-DSP2407
- TMS320LF2407 模拟量输入的编程应用-TMS320LF2407 AIN
Take-minutes-of-a-stopwatch
- 这是根据51单片机学习后自己编的程序，主要是控制51单片机板上数码管来实现秒表的功能-This is based on 51 single chip microcomputer after studying their compiled program, mainly digital tube is 51 single chip microcomputer control board to realize the stopwatch function
DS18B20
- DS18B20驱动程序。本人调试可用，方便简单。-actuace of DS18B20
led
- STC15F2K60S2单片机直接驱动8位共阴数码管，加上拉电阻-STC15F2K60S2 single-chip direct drive 8-bit common digital tube, plus pull resistance