资源列表
fsk
- 用Verilog实现FSK调制，调用IP核实现正弦余弦的调制-Verilog implementation using FSK modulation, called IP core to achieve the modulation sine cosine
test_ad9852
- 使用FPGA来控制DDS信号的产生，从而达到高频信号产生的目的。使用的DDS芯片为AD9852，在QuartusII下编写。-Using the FPGA to control the DDS signal generation, so as to achieve high-frequency signal generation purposes. Use of DDS chip AD9852, in the QuartusII prepared.
software_spi
- Software spi header file using 3 general purpose IO pins of an atmel uc
AD9832AND8402
- 程序可用于产生幅值和频率可变的正弦波，本人测试成功！-Used for generate sine which can change the frequency and amplitude
interrupt_FSM_for_picoblaze
- finite state machine interupt handler for xilinx spartan 3E
kaoqin
- 建议的考勤系统，用于单片机仿真实现对考勤的检查及记忆。-The suggestion for checking attendance system, the realization of single-chip simulation attendance checking and memory.
rcv
- rs232 接受模块 处理 窜信号 分并信号-rs232 verliog receive module
key931
- 这是一个密码锁的vhdl语言实现,其密码为931，连续输入即可开锁-this is a key whose numbei is 931 in vhdl
counter
- 将50MHz时钟信号分频为1Hz,对1Hz方波信号进行计数，并利用4连体数码管进行动态显示-50MHz clock signal at a frequency of 1Hz, to count the 1 Hz square wave signal, and using 4 Siamese digital tube dynamic display
The-various-functions-of-the-counter
- 各种功能的计数器VHDL语言编写，亲自运行，无错-The various functions of the counter VHDL language, personally run error-free
Logarithm
- Logarithm calculating code in VHDL