资源列表
dff_UDP
- verilog实现，UDP描述带有异步复位的正边沿触发D触发器，test测试通过-verilog achieve, UDP asynchronous reset with a descr iption of the fringe is triggered D flip-flop, test test pass
lab_1
- qt2410 test lab for source code
add128
- 128位的地址译码器，在cpld或者fpga上实现兼可-128-bit address decoder, in the CPLD or FPGA implementation and may
couette-b-imp-cran
- Consider flow between a impulsively moving and stationary plate (unsteady Couette flow):1
DA
- 利用DAC0832的单片机输出正弦波信号，高精度，频率、幅度可调 -DAC0832 microcontroller using the output sine wave signal, high precision, frequency, amplitude adjustable
Binary_Multiplier_Binary_Multiplier1.vhd
- its vhdl proggrame for binary multiplication
one_wire
- Simple AVR applcation which uses one wire interface
uart
- C语言uart通讯,包含C51的代码，C语言uart通讯,包含C51的代码-C-uart communication, including the code C51
Dc-motor-speed
- 基于51的直流电机按键控制。通过按键控制电机的转速-51-based DC motor button control. Buttons control the motor speed
lpc-time0-teimcap
- lpc11** 通过对time16位进行timecap的操作程序代码-LPC11** through time16 bit timecap operation program code
guang_module
- TCD1209的驱动程序，可以编译通过的！-TCD1209 driver can be compiled by!
costas
- 基于costas环路的载波同步，使收发时钟频率和相位一致，环路包括四个部分乘法器和低通滤波、鉴相器、环路滤波器和数字振荡器组成-Based on the carrier synchronization of Costas loop, the frequency and phase of the transmit and receive clock is the same. The loop consists of four parts, including the multiplier and