资源列表
IOinitial
- 本程序是关于PIC端口初始化，希望对大家有帮助。-IO INITIAL
dds2
- 同样逻辑分析仪中部分硬件描述语言VHDL做的DDS模块，-The same part of the logic analyzer in VHDL hardware descr iption language modules do DDS,
question4
- Q4 This exercise is to count logic pulses on a single input bit using a Polling technique
asagi_yukari_sayici_entity
- vhdl up down counter, entity,vhdl, good source code
add83coder
- 实现加法器和83译码器的功能！写的很好的verilog程序！-Adder and 83 to achieve the function of the decoder! Verilog to write a good program!
mux41
- 实现VHDL语言4选1通道，在FPGA下实现。-VHDL language to achieve 4 to 1 channel, in the FPGA to achieve.
8lu
- 8路彩灯控制器，运用VHDL语言，EDA技术-8 lantern lantern controller 8 controller 8 lantern controller
DSP1
- DSP Architecture et Application
fasong
- 发送正交码文件。可根据此文件设置任意长度和比重的正交码。-Send orthogonal code files. Can be set to any length and proportion of orthogonal code based on this document.
VGAS
- vga for fpga vhdl so enjoy learn about vhdl
pwm
- VHDL, quartet 2 , FPGA, cyclone II, controllen PWM brightness
mealy_0011_detector
- Key detector a given bit stream-Key detector a given bit stream