资源列表
mccd_capture
- 采用verilog语言，实现视频的采集。通过fpga控制，实现视频逐行采集。-The use of Verilog language, the implementation of video acquisition. Through the FPGA control, achieve progressive video collection.
subtractor3
- Verilog 3bit full subtractor module and tests build with predefined nor gates.
sync
- sucv setting for chipcon 2530
d_ff
- 带置位、清零使能的D触发器以及同步清零D触发器、异步清零D触发器-VHDL，DFF
ff_mul
- 基于rs编码器的verilog伽罗华域乘法器设计-Rs encoder based on Galois field multiplier verilog
Luckey
- VHDL 频率可变的任意波形发生器-vhdl pinlvketiao renyiboxingfashengqi
danpianji
- 使用定时器T0完成1秒和500毫秒方波的输出，用LED灯验证。 使用查询和中断方式实现。 -Use timers T0 seconds and 500 milliseconds to complete one square wave output with LED lights verify. Query and interrupt implementation.
led
- 定义4种模式，完成跑马灯的设计要求，达到要求的四种模式。-architecture one of led is type states is(s0,s1,s2,s3) ------- signal present :states signal q1:std_logic_vector(7 downto 0) signal count:std_logic_vector(3 downto 0)
hongwai
- 红外协议代码用ｖｈｄｌ语言编写，在可编程器件上实现-Infrared agreement with VHDL code language, in programmable devices realize
Division
- Hardware Implementation of Division Algorithm
div
- 一分频，通过计数器原理得到的一分频。十分简洁，适合初学者-A divide, a divide counter principle. Very simple, suitable for beginners
pluse_count
- 以利用FPGA系统时钟分频对定时器进行配置和定时操作。-To take advantage of the FPGA system clock frequency division for timer configuration and operation regularly