资源列表
xiaochexunxian
- arduino控制小车巡线程序 供大家参考-arduino controlled car line inspection program for your reference
song
- 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 梁祝乐曲演奏电路-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Butterfly music concert circuit
code
- it is acode for shift register
PCF8591
- PCF8591: nxp 8-bit A/D and D/A converter, cpu is tms320f28335
view_quartus_simu_on_matlab
- 在进行Quartus仿真时，由于直接用自带的仿真工具无法查看正弦波，将仿真数据另存为tbl格式，用Matlab的程序调用该tbl文件，即可观察波形。当然，利用Modelsim更好。-During Quartus simulation, waveform directly with their own simulation tools can not view the sine wave, Save the simulation data for the tbl format, using the
000
- 用51单片机控制的避障小车程序框架，非常有用，可移植性好-51 microprocessor controlled obstacle avoidance for car application framework, is very useful, portable
Train_8
- 数据段中binb存放一个16位二进制无符号数，将其化成压缩BCD码，存于bcdu单元中-in data segment, binary unsigned data, convert the data in to BCD formate
MIPS_32numbers_32bits
- MIPS架构下的32位32个寄存器组的verilog源码-MIPS architecture 32 32 register banks verilog source
manchester_encoder
- 曼切斯特码解码器verilog程序，已通过ModelSIM仿真，可用-Chester Verilog decoder procedures, has been through the ModelSIM simulation, the available
counter_vhd
- An asynchronous (ripple) counter is a single d-type flip-flop, with its J (data) input fed its own inverted output. This circuit can store one bit, and hence can count zero to one before it overflows (starts over 0). This counter will increment once
ASKMod
- ASK调制信号的verilog VHL设计，在ise中实现了ASK信号的调制解调。-ASK modulation signal verilog VHL design, in ise to achieve the ASK signal modulation and demodulation.
关于NVIC初始化
- 该源码提供了NVIC在K60单片机中的详细初始化例程，可以用于编写相关嵌入式开发程序