资源列表
FINALWORK
- 简易信号发生器 可产生正弦波、方波、三角波、锯齿波 周期可调 verilog-Simple signal generator can produce sine, square, triangle wave, sawtooth-cycle adjustable verilog
ncr
- module to wait 2 clocks for SD card
finaldsamp
- this program basicly showing the effect of downsampling
alu
- 实现五位加法器功能，还有ALU的程序模块！同时有四位全加器的功能模块！-Adder to achieve five functions, as well as program modules ALU! At the same time there are four full-adder modules!
and4
- used for logical and-ing two 1-bit numbers
alu
- 一个简单的四位alu，用max+plusII运行-a simple 4bit alu by vhdl.You can use max+plusII to text it
M8_Interrupt
- ATmege8 中断实验 由我本人亲自测试通过-ATmege8 interrupt experiment tested by me personally! !
MIF_file_of_Sine_Wave_Generator
- 在Quartus的DDS设计中，通常会用到mif或者hex文件存储函数值，被ROM的IP模块调用。本程序是在Matlab环境下，根据所需数据位数和长度自定义mif文件。-Quartus DDS design, usually used in the mif or hex file storage function value, call the ROM of IP modules. This program is in the Matlab environment, according to t
sccb
- OV7670 sccb协议 控制图像的读取操作-The OV7670 sccb protocol control the reading operation of the image
bin2dspdat
- 二进制文件转换为DSP的DAT格式文件的程序段-a program segment convert binary file to dsp dat format file
mux2to1
- 2路选择器 很好很使用的VHDL语言 能够快速的解决问题-2-way selector
Test
- sprtan6 xc6slx45+tms320f28335