资源列表
SingleclocksynchronousdesignmetricCNTR
- 用VHDL 设计的单时钟同步十进制可逆计数器的设计-VHDL design using a single clock synchronization decimal CNTR Design
mux2_1
- 2选1数据选择器，用于数据的切换，vhdl编写，实际使用过-mux2 to 1
4ask
- 数字通信系统4进制振幅键控4ASK信号的调制的VHDL代码-Digital Communication Systems 4 binary amplitude shift keying modulation 4ASK signal VHDL code
trysock
- 扫描host主机端口，查看端口是否有空闲。能否进行连接。目标机器是vxworks-Host host port scan to see whether the ports are free. Able to connect. Target machine is vxworks
dsp4-tms320f2812
- 除法计算：把用除以10的办法二进制数转成BCD码例子-Division calculation: 10 ways to use the binary number divided by the converted BCD code example
screen_1
- 符合avalon总线接口的LED控制软核-Avalon bus interface LED control soft-core
wsm
- 八位数码管的位扫描程序，已在开发板上验证使用-Digital tube scanner, has been verified on the development board to use
counter8
- 8 位 计数器，带使能键和重置键。附带testbench, verilog 环境-8 bit counter
union_float
- 本文件通过使用联合体，解决了C8051不能使用串口收发浮点数的问题-This file by using the Commonwealth to address the C8051 can not use floating-point serial port transceiver problems
m_serial
- m序列产生。3个300阶m序列级联，产生近似随机的数数。输出包括串行输出的随机时钟和并行输出的32位的随机数。-m sequence generation. 3 300 m-order sequence cascade, resulting in an approximate number of random numbers. Output 32 of the random numbers and the parallel clock output comprises serial output
mux
- 二选一数据选择器，可以实现在两个数据中选择一个数据的功能。-Choose one data selector can a data in two data functions.
behavioral-hmwk5
- Design a synchronous circuit which monitors a 3-bit code as the input. If the code has a constant value in four consecutive clock cycles, a flag is activated.