资源列表
Proteus+
- Proteus 仿真实例.包括DS1302时钟、Max7221动态显示、播放音乐、流水灯、字符液晶1602、走马灯等！-Proteus simulation example. Including the DS1302 clock, Max7221 dynamic display, play music, water lights, LCD 1,602 characters, like a revolving door, and so on!
viakple_bsp_v2.321.ce50
- 威盛 wince5.0 bsp 包 for x86 系统, 支持 VT8601 等北桥，详见readme文件-VIA wince5.0 bsp package for x86 systems, such as the North Bridge VT8601 support, See the readme file
LCDTestbasedonSTR71x.Zip
- Lcd test demo code based on St arm mcu
RTOSPlugin_forEWARMv4.30a
- RTOS based STR71x series mcu
ChipDemo
- TI TMS470 series mcu demo code
mouse_demo
- Mouse for USB demo, based on STR710
uCOS-II_2005.06.29
- ARM7 based on STR71x, UCOS migration
multi-sensor
- 多传感器多目标跟踪技术研究,主要研究多传感器多目标跟踪技术-multi-sensor and multi-target tracking technology, principally multi-sensor and multi-target tracking technology
book28888889
- 单片机课程设计 -SCM curriculum design curriculum design SCM SCM SCM curriculum design curriculum design
VERILOGSELE
- 运用always 块设计一个八路数据选择器。要求：每路输入数据与输出数据均为4 位2进制数，当选择开关(至少3 位)或输入数据发生变化时，输出数据也相应地变-always use a block design options for the Eighth Route Army data. Requirements : every road input data and output data are four two-band number, When choosing to switch (a
VERILOGBLOCK
- 在blocking 模块中按如下写法，仿真与综合的结果会有什么样的变化？作出仿真 波形，分析综合结果。 -in blocking module by the following wording, simulation and synthesis of the results will be what kind of changes? Make simulation waveform analysis and comprehensive results.
VERILOGTIME
- 利用10M 的时钟，设计一个单周期的周期波形-use 10M clock, the design of a single-cycle waveform cycle