资源列表
databortfor2410
- 基于ARM920T内核的S3C2410下的databort（数据异常模式）程序，ARM所作-Based on ARM920T core of the S3C2410 databort (data anomaly pattern ) process by ARM
swifor2410
- 基于ARM920T内核的S3C2410下的SWI（软件中断）程序，ARM所作-Based on ARM920T core of the S3C2410 SWI (software interrupt) procedures, ARM made
SimpleforS3C2410
- 注意编译环境：ARM-Linux，这是一个为S3C2410入门者所写的简单但是较全面的源代码，编译时请注意相应参数的修改，学习S3C2410开发，从这里开始！-attention to the build environment : ARM-Linux. This is a S3C2410 for beginners written a simple but comprehensive source code, Please note that compile-time parameter ch
guessnumbergame
- 下载即可运行，适用于初学者学习。 这里是源码。下载到单片机可运行。需要加键盘和显示屏-operation can be downloaded applicable to beginners learning. Here is the source code. SCM can be downloaded to run. Need to increase the keyboard and display
myDoc1
- 本设 计 将 转换结束状态线STS与单片机的P1.7 相连，启动转换信号CE由单 片机的丽和丽相与所得，采用查询方式来读取AD574A的转换结果，由AO来 控制读取高8位和低4位。-the design will change end of the state line STS and SCM P1.7 connected, CE start converting signals from the MCU Laguna and Laguna phase proceeds, using i
vhdlcodes11
- FPGA/CPLD集成开发环境ise的使用详解 示例代码-FPGA / CPLD integrated development environment IDE ise the example code
vhdlcodes10
- FPGA/CPLD集成开发环境ise的使用详解 示例代码10-FPGA / CPLD integrated development environment IDE ise the example code 10
vhdlcodes9
- FPGA/CPLD集成开发环境ise的使用详解 示例代码9-FPGA / CPLD Integrated Development Environment ise Comments on the use of code examples 9
vhdlcodes8
- FPGA/CPLD集成开发环境ise的使用详解 示例代码8-FPGA / CPLD integrated development environment IDE ise the sample code 8
vhdlcodes7
- FPGA/CPLD集成开发环境ise的使用详解 示例代码7-FPGA / CPLD integrated development environment IDE ise the sample code 7
xsi
- verilog 实现帧同步,比较简短的一个程序-verilog achieve frame synchronization, a relatively short procedure
LCDSourcecode
- LCD液晶显示代码，经过调试，实践后可以使用。-LCD display code, after debugging, can be used after the practice.