资源列表
testdct
- 本程序为电磁铁测试程序，输出波形为下面的脉冲形式，最前面一段为高电平（可调） 可调高电平最底分辨率为1MS，最大量程为999MS，后面一部分为高10MS，低20MS脉冲 ___ ___ ___ |___| |___| |___| |___|.|___|.|___|. 高 中 低 ____ 10_ 18_ _ _ _ _ __ | |_| |_| |_| |_| |_| |_| |_| 脉宽可调 小脉冲宽10MS低的部分16MS p1
comic
- 实现TWINS乒乓的对角线运动。 可以看到一对TWINS乒乓球的对角运动轨迹。在液晶显示屏两半显示面中对称的两个乒乓球从角落发出，向对角运动，到对角的角落然后又从头开始，如此循环。 可以按键盘的4键退出到主界面，进行选择进入其它组员模块。-achieve the diagonal movement. Can see a table tennis TWINS the right angle trajectory. The LCD screen shows two semi-symmetri
thetechnologyinruitationofX25045
- 单片机应用系统设计中的看门狗技术控究,简单介绍-SCM application system design technology with the watchdog study, a brief introduction
st72321433HZKey
- st7单片机各个中断程序，包含TimerA解析汽车遥控，串口收发等解码汽车遥控-st7 SCM suspended all procedures, including TimerA analytic car remote control, Serial transceivers, and other remote-control car decoder
ucos_menu_devolopment
- 在ucos环境下实现了一个电子菜单，可以在此基础上进行扩展，生成功能更丰富的菜单-OUT environment in the realization of an electronic menu can be the basis for expansion generating functional richness of the menu
dualportRAM
- 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
kbhookdll
- wince 下的hook 程序 进行系统 GetMessage的拦截，本例进行WM_TEXT 拦截-wince under the hook GetMessage procedures for the interception system, WM_TEXT cases for the interceptor
AD9851_signal_generator
- 用C编写的信号发生器的单片机程序,主要功能是能够接收计算机串口发送的消息,然后根据发送过来的数据来修改信号发生器的输出频率和相位-prepared by the signal generator SCM procedures, Its main function is to receive computer serial transmission of news, According to the data sent over to amend the signal generator outp
sampleVHDL
- 采样等精度测量的VHDL程序．．在xilinx ISE 8.1上验证通过-sampling and other precision measurement of VHDL program. . In xilinx ISE tested through 8.1.
trasmistion
- MSP430通信操作，包括uart,SPI,I2C.等程序 在IAR4.0上验证通过-MSP430 communications operation, including uart, SPI, I2C. procedures in IAR4.0 tested through. .
bujindianjiVHDL
- 步进电机定位控制系统VHDL程序与仿真波形．已经在xilinx ISE 8.1上验证．完全正确．-positioning stepper motor control system procedures and VHDL simulation waveform. Xilinx ISE has tested 8.1. Absolutely correct.
Uart2
- uart的VHDL源代码，包括intface.VHD UART_RX_TAB.VHD UART_INT_TB.VHD等-uart VHDL source code, including intface.VHD UART_RX_TAB.VHD UART_INT_TB. Volume etc.