资源列表
verilog_Manchester
- verilog—Manchester 极为简单的曼彻斯特编解码 verilog实现 分为编码和解码两个部分 通过自己测试 同步异步均正常收发-extremely simple verilog-Manchester Manchester codec verilog achieve synchronization through their own test is divided into two parts of the encoding and decoding Asynchronous w
SD_Card_test
- SD卡读写程序,SPI接口实现，采用verilog hdl实现- SD read and write test
src
- 异步SRAM控制器，已经在DE2板子上测试可用，测试频率50MHz。-Asynchronous SRAM controller, has been on the DE2 board test available test frequency 50MHz.
fft
- Verilog的简单FFT算法，简单，好用-Verilog simple FFT algorithm, simple, easy to use
blauxe_4v8b_2d1e
- 4路数据光端机，光纤传输485或232数据控制球机云台，经过验证无问题-four data link
adc_dac_demo
- 在FPGA芯片上进行AD采集应用开发的良好例程-AD collection good routine application development on the FPGA chip
jbi_22
- 用于CPU模拟JTAG接口来配置altera的FPGA-jam player are used to configure altera fpga
stopwatch-by-verilog-HDL
- 一个基于FPGA用verilog HDL 编写的数字秒表已经LED灯的配合-LED lamp with a digital stopwatch has been prepared based on the FPGA using verilog HDL
emif
- EMIF字符型设备驱动，实现了dm368与FPGA之间的通信，把FPGA当着dm368的一个ram往里面写数据和向外发数据。-The driver of EMIF .
LCD12864-display-chinese
- 利用VHDL进行嵌入式设计编程，利用LCD12864模块显示中文字符-VHDL programming of embedded design, the use of the the LCD12864 module to display Chinese characters
INT_DCT
- Verilog HDL语言实现的整数DCT变换模块。其中包括一维和两维的DCT变换模块各一个。该模块都通过硬件仿真以及FPGA实现后的测试，均满足预期的DCT变换功能。-Integer DCT transfer module with Verilog HDL format. The package includes one 1-D and one 2-D DCT transfer module, which all pass simulation and FPGA evaluation.
MSK
- 最小移频键控(MSK)调制解调技术的原理及应用分析-Minimum Shift Keying (MSK) modulation and demodulation technology principle and application analysis