资源列表
music_player
- 用Verilog语言在FPGA上实现了音乐播放这一功能。预先将音乐《北京欢迎你》转换保存到FPGA的ROM中，由设计的音乐播放器按时序读出数据，予以播放。-Using Verilog language in FPGA realize the function of playing music.The music of "welcome to Beijing" was transformed and saved in FPGA ROM, the data was read by music pl
trivium
- trivium密码算法的 verilog 实现 测试正确-trivium password algorithm verilog test correct
Multiplier
- 一个乘法器的FPGA设计代码 Multiplier-fpga Multiplier
SPI_Master
- 此代码是SPI接口的Master的Verilog源代码，经上板测试是没有问题的，请大家放心使用-This code SPI Interface Master of Verilog source code, there is no problem on board test, please rest assured to use
responder
- 实现四路抢答器功能，主持人可以控制抢答开始，也可以将各个抢答器清零-Responder function to achieve four-way, the host can control the answer in the beginning, you can also clear the various Responder
altera_fft
- verilog实际例子，非常适合初学者学习-verilog practical examples, very suitable for beginners to learn
PipelineSim
- 用verilog编写的简单流水线CPU，指令集根据DLX指令集修改而来。只支持定点操作.-Verilog prepared by the simple lines with a CPU, instruction set modified from under the DLX instruction set. Supports only fixed-point operation.
MII
- 以太网MII芯片配置接口的VHDL设计，配置PHY芯片的模块设计-Ethernet MII chip configuration interface VHDL design, configuration PHY chip module design
FPGAscp1000SPI
- FPGA与 scp 1000压力传感器SPI 接口描述，比较有难度，该代码可以综合，用verilog 写的。-FPGA and scp 1000 SPI
FLASH_read
- 对spi接口的flash操作，用VHDL语言实现，read控制，串行输入，可以1位、2位、4位读出-Spi interface on the flash operation, with the VHDL language, read control, serial input, to one, two, four read
OneWireMaster
- 美信onewire总线IP core,带验证激励-MAXIM DS1WM Synthesizable 1-Wire Bus Master IP core.
hash
- 基于伽罗瓦域的ghash核，用于GCM。其中，128位伽罗瓦域乘法器使用的是多项式算法。经验证，可综合，供参考。-Galois field based on the nuclear ghash