资源列表
decoder
- vhdl code for decoder and detemines the basic mechanism of gates of decoder
par_addsub
- adder subtreactor verilog code
Coder
- 码盘判别方向及计数 用Verilog语言编写-Determine the direction of the encoder and counting with the Verilog language
mux_3_conditional
- implementation of multiplexer using conditional operator
write
- 使用golang生成一个coe文件，初始化rom。其中随机产生10000个数值作为初始化值-Use golang generate a coe file to initialize rom. Wherein the randomly generated value as the initial value 10000
IIC_dev
- IIC传输，实际遇到的开发问题处理。很有借鉴意义，避免走弯路哦-IIC transmission, practical problems encountered in the development process. Referential significance, oh avoid detours
clk_div
- Clock division document
10010
- verilog实现序列10010检测-verilog to achieve detection of sequence 10010
Demultiplexer
- 解复用器，很好很强大的程序 解复用器，很好很强大的程序-DEscr iptION : Demultiplexer -- Width: 8 -- Number of terminals: 4 -- Output enable active: HIGH -- Output active : HIGH
zhuan2_10
- 用于FPGA/CPLD开发的2进制转换成BCD码的程序。-For FPGA/CPLD development of two binary into BCD code procedures.
rtl
- 基于verilog的FPGA新型跑马灯程序设计-led run
lcd1062
- 通过PIC16F877A控制LCD1062，从而实现液晶显示。-By PIC16F877A control LCD1062, in order to achieve liquid crystal display.