资源列表
USB_SLAVE_700AN_RD
- 基于verilog 代码的USB2.0同步FIFO读代码-USB2.0 syn FIFO read
zpu_wb_top
- ZPU程序文件，供ZPU接口使用，用verilogHDL编写-ZPU program files for ZPU interface, written with verilogHDL
UART_1
- ＳＴＣ单片机的串口模块可以采用Ｔ１定时器作为它的波特率发生器，同时其内部也集成了一个独立波特率发生器作为串口的波特率发生器，本例子采用的是常用的Ｔ１定时器作为它的波特率发生器-STC microcontroller serial port T1 timer module can be used as its baud rate generator, while its interior also incorporates an independent Baud Rate Generator as
stopwatch-based-on-VHDL
- 基于VHDL的电子秒表的设计，使用VHDL语言描述一个秒表电路，利用QuantusII软件进行源程序设计，编译，仿真，最后形成下载文件下载至装有FPGA芯片的实验箱，进行硬件测试，要求实现秒表功能。-Design of electronic stopwatch based on VHDL
scan_led
- 每个时钟，计数时间，实现8的扫描显示，在数码管上依次显示13579bdf，可以选择EDA实验箱，FPGA EP1C6Q240C8。-Each clock, counting time, achieve 8 scan display, turn on the digital tube display 13579BDF, can choose EDA experimental box, FPGA EP1C6Q240C8.
uart_rx
- 串口接收模块代码，根据设定的串口波特率，可以正确接收串口的数据-Serial receive module code, according to the set baud rate, serial data can be correctly received
dac_ctl
- 主要功能为控制DAC芯片，来控制压控晶体振荡器，产生所需的时钟信号。-Mainly used for DAC control VCO to generate the required clock signal can be used directly.
led
- vhdl实现“PLD电子技术”（文字显示）
FSKdemodulation
- 基于VHDL硬件描述语言对FSK调制信号进行解调 -A VHDL program to realize the FSK demodulation of digital signals
ASPfinalwithoutCLK
- A FIFO PROGRAM USING VHDL, USING ASP PROTOCOL-A FIFO PROGRAM USING VHDL, USING ASP PROTOCOL..
my_func_pkg
- multiply vhdl package code
keymatrix
- assembly key matrix with LCD