资源列表
fulladder_TB
- fulladder test bench
multiplier_TB
- multiplier testbench
devided
- 一个16位除8位的除法器，能够输出余数和商。(In addition to a 16 bit 8 bit divider, can output the remainder and quotient.by stan)
VGA
- vga code for fpga 3s500e spartan xilinx code verilog tutorial video graphics array in verilog interfacing with fpga xilins spattan 3e very easy to learn
keyboard
- 通过ps2口实现键盘的链接，对FPGA进行输入。(Through the PS2 port to achieve the keyboard link, the FPGA input.)
full_adder
- 全加器，可以实现数据的加法运算，有来自低位的进位和向高位的进位。(Full adder, data can be added to the operation, there are low from the carry and to the high carry.)
第5章_QuartusII应用向导(原理图输入方法)1
- I hope the PDF file I shared is very useful for you.
第3章__Quartus_II原理图输入法深入
- I hope the PDF file I shared is very useful for you. And I also wish I can learn some useful knowledge from this web.
第2章_Quartus_II原理图输入
- I hope the PDF file I shared is very useful for your job. Thanks
第2章_Quartus_II_使用方法
- I hope the PDF file I shared is very useful for your work. Thanks
DE2_CAMERA
- DE2 camera interface code
60jishuqi (2)
- 这是一个可以记到60的计数器，可用于数字钟层次化设计。(This is a counter that can be recorded to 60, and can be used for the hierarchical design of digital clock.)