资源列表
vhdl_examples
- vhdl语言例程集锦，大量丰富的程序代码，对于VHDL学习很有帮助-VHDL language routines magazines, large variety of code for VHDL helpful learning
CPLD_CCD
- 实现基于CPLD的CCD采集系统设计源码-based CPLD CCD Acquisition System Design FOSS
MAX_II_board_schematics
- Altera MAX II 开发板原理图-Altera's MAX II development board schematics
air_controller
- 此为一个空调控制器，是利用FPGA来实现的，他能够完成对室内温度的调节。-this as an air-conditioning controller, is to use the FPGA to realize that he can complete the indoor temperature adjustment.
sdramcore
- sdram控制的内核，高手编的，已经调试过了，没有错误-SDRAM control of the kernel, the top series, has been tuned, no errors
source_verilog
- verilog shi 实现的加法器（8位）适用于初学asic -Verilog realized Adder (8) applies to beginners blends
n_dc_motor
- vhdl实现的直流电机控制器 通用程序 对不同fpga/cpld，可能需要修改部分源代码。-VHDL achieved DC Motor Controller General of different procedures they simply / cpld. may need to amend some source code.
TI6713DSKVHDL
- TI6713浮点DSP的DSK的VHDL。比较全面。可以编译运行。-TI6713 floating-point DSP DSK VHDL. More comprehensive. Compiler can run.
FIR_1
- FIR滤波器的verilog实现，实现6级流水线的程序设计。-FIR filter Verilog, has implemented six lines of program design.
vhdlprogram
- 用复杂可编程逻辑器件(CPLD)实现的数字钟控系统-with complex programmable logic devices (CPLD) with a digital clock control system
pluse_delay
- 利用VHDL语言实现单稳触发电路，稳态时间为系统时钟的整数倍。-using VHDL-trigger circuit stability, steady time for the whole system clock several times.
ccpu
- 这个是用VERILOG做的一个8位功能很弱的CPU-this is a done VERILOG eight functional weak CPU