资源列表
HMC835-330-665M
- HMC835单点频配置软件，寄存器配置，分配器配置等。(HMC835 single point frequency configuration software)
常用晶振器件图SCH
- 常用的有源晶振封装库和原理图库，AD环境。(AD environment commonly used active crystal package library and schematic library)
i2c_ctrl_master1
- I2C总线控制器，master端，控制寄存器读写(I2C Master controller)
3-14读MS5837数据_子函数(可用)
- TM4C123GH6PM读取MS5837数据(read the data from MS5837 to TM4C123GH6PM,the program is tested)
火灾报警程序代码
- 基于单片机设计的火灾报警程序，用的是51单片机和DS1820温度传感器，以及其他元器件(Fire alarm program based on SCM.51 SCM and DS 1820 temperature sensor, and other components)
dpll源程序
- 一种设计数字锁相环的思路，包含异或鉴相器、k模可逆计数器、脉冲加减计数器、N分频器等，实现相位的锁定。(A design of digital phase locked loop (PLL) consists of a phase discriminator, a K mode reversible counter, a pulse addition and subtraction counter, a N frequency divider and so on, to lock the pha
1.hex
- 用八块LED显示屏显示从0时0分0秒到23时59分59秒的变化来计时(Timing with eight LED screens showing changes from 00:00:00 to 23:59:59)
8Bit_ALU
- logisim设计 实现 加 减 与 或 异或 或非(Logisim design implements add and subtract and or exclusive or no)
Cascaded_EDAFs
- optical cascaded EDAF amplifiers design
Arudino Ping sensor code
- Arudino Ping sensor code,It is used for sensor interface with project like distance estimation tool and blind stick projects,It is very useful
control
- implementation of a control system analysis.
dpll
- 数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法-Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis