资源列表
tuxiangfenjie
- 小波变换，用于图像分解，使图像分为几层，并分析每层的信号。-Wavelet transform for image decomposition, the image is divided into several layers, and analyze each of the signal.
wavalet
- 通过小波变换对图像信号进行分解，去噪，压缩再重构，得到处理后的图像-Images using wavelet transform signal decomposition, denoising, compression and then reconstructed to obtain the processed image
Face-recognition
- 本文针对人脸图像的特点，选取一组Gabor 小波核，并用这组Gabor 小波核对人脸图像进行Gabor 小波变换，提取人脸 图像的有效信息。在此基础上，用2DPCA 对Gabor 小波提取的 数据矩阵进行降维，最后用最近邻法对人脸进行分类。-In this paper, the characteristics of face images, select a set of Gabor wavelet kernel, and check with this set of Gabor wav
EZW2
- VC++基于小波变换的数字图像压缩源代码，基于嵌入式零树编码方式的图像压缩。-VC++ based on wavelet transform of digital image compression source code, based on embedded zerotree coding for image compression.
WAVELET2D
- 用VC++实现的二维小波变换的BMP格式的数字图像处理-VC++ implementation with two-dimensional wavelet transform BMP format, digital image processing
wavelet
- 最好用的小波程序，包括小波应用到图象处理，第二代小波处理等，程序全部可用。-Best use of wavelet procedures, including wavelet applied to image processing, the second generation wavelet processing, all the procedures available.
sin
- 小波变换 bd3，sym8，小波去噪，两种方法对比-Transform bd3, sym8, wavelet denoising, compared two methods
utf-8__proje
- eeg fourier transform
sinmpletest
- 图像的二维分解与重构程序,只进行了一层的小波变换, 还有配合程序downspl和upspl-Two-dimensional image decomposition and reconstruction process, only carried out a layer of the wavelet transform, as well as with the procedures and upspl downspl
ztree-sprljan
- spiht ezw by sprljan. Consist of fastcode.exe, fastdecd.exe, codetree.exe, decdtree.exe ((c)1995, 1996 Amir Said & William A. Pearlman http://www.cipr.rpi.edu/research/SPIHT/spiht3.html)-spiht ezw by sprljan. Consist of fastcode.exe, fastdecd.
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- 9/7提升小波变换中奇偶分裂步、预测步、边界延拓处理和模块测试平台的Verilog代码描述：-9/7 lifting wavelet transform in odd and even split-step, prediction step, boundary extension process and module test platform described in Verilog code:
VerilogHDL
- 9/7提升小波变换中奇偶分裂步、预测步、边界延拓处理和模块测试平台的Verilog代码描述：-9/7 lifting wavelet transform in odd and even split-step, prediction step, boundary extension process and module test platform described in Verilog code: