文件名称:bram_delay
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- 上传时间:2012-11-16
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文件大小:1.37mb
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Verilog编写的代码,单口RAM用程序控制地址,而不是在仿真文件里面控制地址-Verilog code is written, single-port RAM with the process control address, rather than inside the control address of the simulation file
相关搜索: verilog br
ram vhdl
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下载文件列表
bram_delay/.lso
bram_delay/blk_mem_gen_ds512.pdf
bram_delay/blk_mem_gen_release_notes.txt
bram_delay/bram_16.asy
bram_delay/bram_16.ngc
bram_delay/bram_16.sym
bram_delay/bram_16.v
bram_delay/bram_16.veo
bram_delay/bram_16.vhd
bram_delay/bram_16.vho
bram_delay/bram_16.xco
bram_delay/bram_16_blk_mem_gen_v2_4_xst_1.lso
bram_delay/bram_16_blk_mem_gen_v2_4_xst_1_vhdl.prj
bram_delay/bram_16_flist.txt
bram_delay/bram_16_readme.txt
bram_delay/bram_16_xmdf.tcl
bram_delay/bram_delay.doc
bram_delay/bram_delay.ise
bram_delay/bram_delay.ise_ISE_Backup
bram_delay/bram_delay.prj
bram_delay/bram_delay.restore
bram_delay/bram_delay.stx
bram_delay/bram_delay.v
bram_delay/bram_delay.xst
bram_delay/bram_delay_summary.html
bram_delay/isim/temp/hdllib.ref
bram_delay/isim/temp/hdpdeps.ref
bram_delay/isim/temp/vlg06/tb__bram__delay__v.bin
bram_delay/isim/temp/vlg08/bram__16.bin
bram_delay/isim/temp/vlg2D/glbl.bin
bram_delay/isim/temp/vlg48/bram__delay.bin
bram_delay/isim/work/bram__16/bram__16.h
bram_delay/isim/work/bram__16/mingw/bram__16.obj
bram_delay/isim/work/bram__delay/bram__delay.h
bram_delay/isim/work/bram__delay/mingw/bram__delay.obj
bram_delay/isim/work/glbl/glbl.h
bram_delay/isim/work/glbl/mingw/glbl.obj
bram_delay/isim/work/hdllib.ref
bram_delay/isim/work/hdpdeps.ref
bram_delay/isim/work/tb__bram__delay__v/mingw/tb__bram__delay__v.obj
bram_delay/isim/work/tb__bram__delay__v/tb__bram__delay__v.h
bram_delay/isim/work/tb__bram__delay__v/xsimtb__bram__delay__v.cpp
bram_delay/isim/work/tst__bram__delay__v/mingw/tst__bram__delay__v.obj
bram_delay/isim/work/tst__bram__delay__v/tst__bram__delay__v.h
bram_delay/isim/work/tst__bram__delay__v/xsimtst__bram__delay__v.cpp
bram_delay/isim/work/vlg06/tb__bram__delay__v.bin
bram_delay/isim/work/vlg08/bram__16.bin
bram_delay/isim/work/vlg2D/glbl.bin
bram_delay/isim/work/vlg48/bram__delay.bin
bram_delay/isim/work/vlg7B/tst__bram__delay__v.bin
bram_delay/isim/xilinxcorelib_ver.auxlib/hdllib.ref
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4/mingw/_b_l_k___m_e_m___g_e_n___v2__4.obj
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4/_b_l_k___m_e_m___g_e_n___v2__4.h
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4__output__stage/mingw/_b_l_k___m_e_m___g_e_n___v2__4__output__stage.obj
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4__output__stage/_b_l_k___m_e_m___g_e_n___v2__4__output__stage.h
bram_delay/isim.cmd
bram_delay/isim.hdlsourcefiles
bram_delay/isim.log
bram_delay/isim.tmp_save/_1
bram_delay/isimwavedata.xwv
bram_delay/simulate_dofile.log
bram_delay/simulate_dofile.log_back
bram_delay/tb_bram_delay.v
bram_delay/tb_bram_delay_v_beh.prj
bram_delay/tb_bram_delay_v_isim_beh.exe
bram_delay/tb_bram_delay_v_isim_beh.wfs
bram_delay/tb_bram_delay_v_stx.prj
bram_delay/templates/coregen.xml
bram_delay/tst_bram_delay.v
bram_delay/tst_bram_delay_v_isim_beh.wfs
bram_delay/xilinxsim.ini
bram_delay/xst/work/hdllib.ref
bram_delay/xst/work/vlg48/bram__delay.bin
bram_delay/_xmsgs/fuse.xmsgs
bram_delay/_xmsgs/xst.xmsgs
bram_delay/__ISE_repository_bram_delay.ise_.lock
bram_delay/isim/work/bram__16/mingw
bram_delay/isim/work/bram__delay/mingw
bram_delay/isim/work/glbl/mingw
bram_delay/isim/work/tb__bram__delay__v/mingw
bram_delay/isim/work/tst__bram__delay__v/mingw
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4/mingw
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4__output__stage/mingw
bram_delay/isim/temp/vlg06
bram_delay/isim/temp/vlg08
bram_delay/isim/temp/vlg2D
bram_delay/isim/temp/vlg48
bram_delay/isim/work/bram__16
bram_delay/isim/work/bram__delay
bram_delay/isim/work/glbl
bram_delay/isim/work/tb__bram__delay__v
bram_delay/isim/work/tst__bram__delay__v
bram_delay/isim/work/vlg06
bram_delay/isim/work/vlg08
bram_delay/isim/work/vlg2D
bram_delay/isim/work/vlg48
bram_delay/isim/work/vlg7B
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4__output__stage
bram_delay/xst/work/vlg48
bram_delay/isim/temp
bram_delay/isim/work
bram_delay/isim/xilinxcorelib_ver.auxlib
bram_delay/tmp/_cg
bram_delay/xst/projnav.tmp
bram_delay/xst/work
bram_delay/isim
bram_delay/isim.tmp_save
bram_delay/templates
bram_delay/tmp
bram_delay/xst
bram_delay/_xmsgs
bram_delay
bram_delay/blk_mem_gen_ds512.pdf
bram_delay/blk_mem_gen_release_notes.txt
bram_delay/bram_16.asy
bram_delay/bram_16.ngc
bram_delay/bram_16.sym
bram_delay/bram_16.v
bram_delay/bram_16.veo
bram_delay/bram_16.vhd
bram_delay/bram_16.vho
bram_delay/bram_16.xco
bram_delay/bram_16_blk_mem_gen_v2_4_xst_1.lso
bram_delay/bram_16_blk_mem_gen_v2_4_xst_1_vhdl.prj
bram_delay/bram_16_flist.txt
bram_delay/bram_16_readme.txt
bram_delay/bram_16_xmdf.tcl
bram_delay/bram_delay.doc
bram_delay/bram_delay.ise
bram_delay/bram_delay.ise_ISE_Backup
bram_delay/bram_delay.prj
bram_delay/bram_delay.restore
bram_delay/bram_delay.stx
bram_delay/bram_delay.v
bram_delay/bram_delay.xst
bram_delay/bram_delay_summary.html
bram_delay/isim/temp/hdllib.ref
bram_delay/isim/temp/hdpdeps.ref
bram_delay/isim/temp/vlg06/tb__bram__delay__v.bin
bram_delay/isim/temp/vlg08/bram__16.bin
bram_delay/isim/temp/vlg2D/glbl.bin
bram_delay/isim/temp/vlg48/bram__delay.bin
bram_delay/isim/work/bram__16/bram__16.h
bram_delay/isim/work/bram__16/mingw/bram__16.obj
bram_delay/isim/work/bram__delay/bram__delay.h
bram_delay/isim/work/bram__delay/mingw/bram__delay.obj
bram_delay/isim/work/glbl/glbl.h
bram_delay/isim/work/glbl/mingw/glbl.obj
bram_delay/isim/work/hdllib.ref
bram_delay/isim/work/hdpdeps.ref
bram_delay/isim/work/tb__bram__delay__v/mingw/tb__bram__delay__v.obj
bram_delay/isim/work/tb__bram__delay__v/tb__bram__delay__v.h
bram_delay/isim/work/tb__bram__delay__v/xsimtb__bram__delay__v.cpp
bram_delay/isim/work/tst__bram__delay__v/mingw/tst__bram__delay__v.obj
bram_delay/isim/work/tst__bram__delay__v/tst__bram__delay__v.h
bram_delay/isim/work/tst__bram__delay__v/xsimtst__bram__delay__v.cpp
bram_delay/isim/work/vlg06/tb__bram__delay__v.bin
bram_delay/isim/work/vlg08/bram__16.bin
bram_delay/isim/work/vlg2D/glbl.bin
bram_delay/isim/work/vlg48/bram__delay.bin
bram_delay/isim/work/vlg7B/tst__bram__delay__v.bin
bram_delay/isim/xilinxcorelib_ver.auxlib/hdllib.ref
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4/mingw/_b_l_k___m_e_m___g_e_n___v2__4.obj
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4/_b_l_k___m_e_m___g_e_n___v2__4.h
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4__output__stage/mingw/_b_l_k___m_e_m___g_e_n___v2__4__output__stage.obj
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4__output__stage/_b_l_k___m_e_m___g_e_n___v2__4__output__stage.h
bram_delay/isim.cmd
bram_delay/isim.hdlsourcefiles
bram_delay/isim.log
bram_delay/isim.tmp_save/_1
bram_delay/isimwavedata.xwv
bram_delay/simulate_dofile.log
bram_delay/simulate_dofile.log_back
bram_delay/tb_bram_delay.v
bram_delay/tb_bram_delay_v_beh.prj
bram_delay/tb_bram_delay_v_isim_beh.exe
bram_delay/tb_bram_delay_v_isim_beh.wfs
bram_delay/tb_bram_delay_v_stx.prj
bram_delay/templates/coregen.xml
bram_delay/tst_bram_delay.v
bram_delay/tst_bram_delay_v_isim_beh.wfs
bram_delay/xilinxsim.ini
bram_delay/xst/work/hdllib.ref
bram_delay/xst/work/vlg48/bram__delay.bin
bram_delay/_xmsgs/fuse.xmsgs
bram_delay/_xmsgs/xst.xmsgs
bram_delay/__ISE_repository_bram_delay.ise_.lock
bram_delay/isim/work/bram__16/mingw
bram_delay/isim/work/bram__delay/mingw
bram_delay/isim/work/glbl/mingw
bram_delay/isim/work/tb__bram__delay__v/mingw
bram_delay/isim/work/tst__bram__delay__v/mingw
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4/mingw
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4__output__stage/mingw
bram_delay/isim/temp/vlg06
bram_delay/isim/temp/vlg08
bram_delay/isim/temp/vlg2D
bram_delay/isim/temp/vlg48
bram_delay/isim/work/bram__16
bram_delay/isim/work/bram__delay
bram_delay/isim/work/glbl
bram_delay/isim/work/tb__bram__delay__v
bram_delay/isim/work/tst__bram__delay__v
bram_delay/isim/work/vlg06
bram_delay/isim/work/vlg08
bram_delay/isim/work/vlg2D
bram_delay/isim/work/vlg48
bram_delay/isim/work/vlg7B
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4
bram_delay/isim/xilinxcorelib_ver.auxlib/_b_l_k___m_e_m___g_e_n___v2__4__output__stage
bram_delay/xst/work/vlg48
bram_delay/isim/temp
bram_delay/isim/work
bram_delay/isim/xilinxcorelib_ver.auxlib
bram_delay/tmp/_cg
bram_delay/xst/projnav.tmp
bram_delay/xst/work
bram_delay/isim
bram_delay/isim.tmp_save
bram_delay/templates
bram_delay/tmp
bram_delay/xst
bram_delay/_xmsgs
bram_delay
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