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clock/clock.ise_ISE_Backup
clock/clock.restore
clock/isim/temp/hdllib.ref
clock/isim/temp/hdpdeps.ref
clock/isim/temp/vlg1E/real__time__clk__verilog.bin
clock/isim/temp/vlg2D/glbl.bin
clock/isim/work/glbl/glbl.h
clock/isim/work/glbl/mingw/glbl.obj
clock/isim/work/hdllib.ref
clock/isim/work/hdpdeps.ref
clock/isim/work/real__time__clk__verilog/mingw/real__time__clk__verilog.obj
clock/isim/work/real__time__clk__verilog/real__time__clk__verilog.h
clock/isim/work/real__time__clk__verilog/xsimreal__time__clk__verilog.cpp
clock/isim/work/vlg1E/real__time__clk__verilog.bin
clock/isim/work/vlg2D/glbl.bin
clock/isim.cmd
clock/isim.hdlsourcefiles
clock/isim.log
clock/isim.tmp_save/_1
clock/isimwavedata.xwv
clock/real_time_clk_verilog.v
clock/real_time_clk_verilog_beh.prj
clock/real_time_clk_verilog_isim_beh.exe
clock/real_time_clk_verilog_isim_beh.wfs
clock/real_time_clk_verilog_stx.prj
clock/real_time_clk_verilog_summary.html
clock/simulate_dofile.log
clock/xilinxsim.ini
clock/_xmsgs/fuse.xmsgs
clock/__ISE_repository_clock.ise_.lock
clock/isim/work/glbl/mingw
clock/isim/work/real__time__clk__verilog/mingw
clock/isim/temp/vlg1E
clock/isim/temp/vlg2D
clock/isim/work/glbl
clock/isim/work/real__time__clk__verilog
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clock/isim/work/vlg2D
clock/isim/temp
clock/isim/work
clock/isim
clock/isim.tmp_save
clock/_xmsgs
clock