文件名称:verilog_seg7
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- 上传时间:2012-11-16
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文件大小:294.09kb
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买的Altra公司的一款Max II EPM1270T144的电路板,其中的一个用Verilog HDL 编写的驱动数码管的程序,完全可用。-Altra Inc. bought a Max II EPM1270T144 circuit board, one written in Verilog HDL using the digital controls process-driven, fully available.
相关搜索: epm1270t144
(系统自动生成,下载前可以参看下载内容)
下载文件列表
verilog_seg7/addcont.bsf
verilog_seg7/addcont.v
verilog_seg7/bin27seg.bsf
verilog_seg7/bin27seg.v
verilog_seg7/db/cntr_mad.tdf
verilog_seg7/db/verilog_seg7.(0).cnf.cdb
verilog_seg7/db/verilog_seg7.(0).cnf.hdb
verilog_seg7/db/verilog_seg7.(1).cnf.cdb
verilog_seg7/db/verilog_seg7.(1).cnf.hdb
verilog_seg7/db/verilog_seg7.(2).cnf.cdb
verilog_seg7/db/verilog_seg7.(2).cnf.hdb
verilog_seg7/db/verilog_seg7.(3).cnf.cdb
verilog_seg7/db/verilog_seg7.(3).cnf.hdb
verilog_seg7/db/verilog_seg7.(4).cnf.cdb
verilog_seg7/db/verilog_seg7.(4).cnf.hdb
verilog_seg7/db/verilog_seg7.(5).cnf.cdb
verilog_seg7/db/verilog_seg7.(5).cnf.hdb
verilog_seg7/db/verilog_seg7.(6).cnf.cdb
verilog_seg7/db/verilog_seg7.(6).cnf.hdb
verilog_seg7/db/verilog_seg7.(7).cnf.cdb
verilog_seg7/db/verilog_seg7.(7).cnf.hdb
verilog_seg7/db/verilog_seg7.asm.qmsg
verilog_seg7/db/verilog_seg7.asm_labs.ddb
verilog_seg7/db/verilog_seg7.cbx.xml
verilog_seg7/db/verilog_seg7.cmp.cdb
verilog_seg7/db/verilog_seg7.cmp.hdb
verilog_seg7/db/verilog_seg7.cmp.qrpt
verilog_seg7/db/verilog_seg7.cmp.rdb
verilog_seg7/db/verilog_seg7.cmp.tdb
verilog_seg7/db/verilog_seg7.cmp0.ddb
verilog_seg7/db/verilog_seg7.dbp
verilog_seg7/db/verilog_seg7.db_info
verilog_seg7/db/verilog_seg7.eco.cdb
verilog_seg7/db/verilog_seg7.fit.qmsg
verilog_seg7/db/verilog_seg7.hier_info
verilog_seg7/db/verilog_seg7.hif
verilog_seg7/db/verilog_seg7.map.cdb
verilog_seg7/db/verilog_seg7.map.hdb
verilog_seg7/db/verilog_seg7.map.qmsg
verilog_seg7/db/verilog_seg7.pre_map.cdb
verilog_seg7/db/verilog_seg7.pre_map.hdb
verilog_seg7/db/verilog_seg7.psp
verilog_seg7/db/verilog_seg7.rtlv.hdb
verilog_seg7/db/verilog_seg7.rtlv_sg.cdb
verilog_seg7/db/verilog_seg7.rtlv_sg_swap.cdb
verilog_seg7/db/verilog_seg7.sgdiff.cdb
verilog_seg7/db/verilog_seg7.sgdiff.hdb
verilog_seg7/db/verilog_seg7.signalprobe.cdb
verilog_seg7/db/verilog_seg7.sld_design_entry.sci
verilog_seg7/db/verilog_seg7.sld_design_entry_dsc.sci
verilog_seg7/db/verilog_seg7.syn_hier_info
verilog_seg7/db/verilog_seg7.tan.qmsg
verilog_seg7/lpm_counter0.bsf
verilog_seg7/lpm_counter0.cmp
verilog_seg7/lpm_counter0.vhd
verilog_seg7/lpm_counter0_wave0.jpg
verilog_seg7/lpm_counter0_waveforms.html
verilog_seg7/lpm_counter1.bsf
verilog_seg7/lpm_counter1.cmp
verilog_seg7/lpm_counter1.vhd
verilog_seg7/lpm_counter1_wave0.jpg
verilog_seg7/lpm_counter1_waveforms.html
verilog_seg7/segmain.bsf
verilog_seg7/segmain.v
verilog_seg7/setup.tcl
verilog_seg7/subcont.bsf
verilog_seg7/subcont.v
verilog_seg7/verilog_seg7.asm.rpt
verilog_seg7/verilog_seg7.bdf
verilog_seg7/verilog_seg7.done
verilog_seg7/verilog_seg7.fit.eqn
verilog_seg7/verilog_seg7.fit.rpt
verilog_seg7/verilog_seg7.fit.summary
verilog_seg7/verilog_seg7.flow.rpt
verilog_seg7/verilog_seg7.map.eqn
verilog_seg7/verilog_seg7.map.rpt
verilog_seg7/verilog_seg7.map.summary
verilog_seg7/verilog_seg7.pin
verilog_seg7/verilog_seg7.pof
verilog_seg7/verilog_seg7.qpf
verilog_seg7/verilog_seg7.qsf
verilog_seg7/verilog_seg7.qws
verilog_seg7/verilog_seg7.tan.rpt
verilog_seg7/verilog_seg7.tan.summary
verilog_seg7/db
verilog_seg7
verilog_seg7/addcont.v
verilog_seg7/bin27seg.bsf
verilog_seg7/bin27seg.v
verilog_seg7/db/cntr_mad.tdf
verilog_seg7/db/verilog_seg7.(0).cnf.cdb
verilog_seg7/db/verilog_seg7.(0).cnf.hdb
verilog_seg7/db/verilog_seg7.(1).cnf.cdb
verilog_seg7/db/verilog_seg7.(1).cnf.hdb
verilog_seg7/db/verilog_seg7.(2).cnf.cdb
verilog_seg7/db/verilog_seg7.(2).cnf.hdb
verilog_seg7/db/verilog_seg7.(3).cnf.cdb
verilog_seg7/db/verilog_seg7.(3).cnf.hdb
verilog_seg7/db/verilog_seg7.(4).cnf.cdb
verilog_seg7/db/verilog_seg7.(4).cnf.hdb
verilog_seg7/db/verilog_seg7.(5).cnf.cdb
verilog_seg7/db/verilog_seg7.(5).cnf.hdb
verilog_seg7/db/verilog_seg7.(6).cnf.cdb
verilog_seg7/db/verilog_seg7.(6).cnf.hdb
verilog_seg7/db/verilog_seg7.(7).cnf.cdb
verilog_seg7/db/verilog_seg7.(7).cnf.hdb
verilog_seg7/db/verilog_seg7.asm.qmsg
verilog_seg7/db/verilog_seg7.asm_labs.ddb
verilog_seg7/db/verilog_seg7.cbx.xml
verilog_seg7/db/verilog_seg7.cmp.cdb
verilog_seg7/db/verilog_seg7.cmp.hdb
verilog_seg7/db/verilog_seg7.cmp.qrpt
verilog_seg7/db/verilog_seg7.cmp.rdb
verilog_seg7/db/verilog_seg7.cmp.tdb
verilog_seg7/db/verilog_seg7.cmp0.ddb
verilog_seg7/db/verilog_seg7.dbp
verilog_seg7/db/verilog_seg7.db_info
verilog_seg7/db/verilog_seg7.eco.cdb
verilog_seg7/db/verilog_seg7.fit.qmsg
verilog_seg7/db/verilog_seg7.hier_info
verilog_seg7/db/verilog_seg7.hif
verilog_seg7/db/verilog_seg7.map.cdb
verilog_seg7/db/verilog_seg7.map.hdb
verilog_seg7/db/verilog_seg7.map.qmsg
verilog_seg7/db/verilog_seg7.pre_map.cdb
verilog_seg7/db/verilog_seg7.pre_map.hdb
verilog_seg7/db/verilog_seg7.psp
verilog_seg7/db/verilog_seg7.rtlv.hdb
verilog_seg7/db/verilog_seg7.rtlv_sg.cdb
verilog_seg7/db/verilog_seg7.rtlv_sg_swap.cdb
verilog_seg7/db/verilog_seg7.sgdiff.cdb
verilog_seg7/db/verilog_seg7.sgdiff.hdb
verilog_seg7/db/verilog_seg7.signalprobe.cdb
verilog_seg7/db/verilog_seg7.sld_design_entry.sci
verilog_seg7/db/verilog_seg7.sld_design_entry_dsc.sci
verilog_seg7/db/verilog_seg7.syn_hier_info
verilog_seg7/db/verilog_seg7.tan.qmsg
verilog_seg7/lpm_counter0.bsf
verilog_seg7/lpm_counter0.cmp
verilog_seg7/lpm_counter0.vhd
verilog_seg7/lpm_counter0_wave0.jpg
verilog_seg7/lpm_counter0_waveforms.html
verilog_seg7/lpm_counter1.bsf
verilog_seg7/lpm_counter1.cmp
verilog_seg7/lpm_counter1.vhd
verilog_seg7/lpm_counter1_wave0.jpg
verilog_seg7/lpm_counter1_waveforms.html
verilog_seg7/segmain.bsf
verilog_seg7/segmain.v
verilog_seg7/setup.tcl
verilog_seg7/subcont.bsf
verilog_seg7/subcont.v
verilog_seg7/verilog_seg7.asm.rpt
verilog_seg7/verilog_seg7.bdf
verilog_seg7/verilog_seg7.done
verilog_seg7/verilog_seg7.fit.eqn
verilog_seg7/verilog_seg7.fit.rpt
verilog_seg7/verilog_seg7.fit.summary
verilog_seg7/verilog_seg7.flow.rpt
verilog_seg7/verilog_seg7.map.eqn
verilog_seg7/verilog_seg7.map.rpt
verilog_seg7/verilog_seg7.map.summary
verilog_seg7/verilog_seg7.pin
verilog_seg7/verilog_seg7.pof
verilog_seg7/verilog_seg7.qpf
verilog_seg7/verilog_seg7.qsf
verilog_seg7/verilog_seg7.qws
verilog_seg7/verilog_seg7.tan.rpt
verilog_seg7/verilog_seg7.tan.summary
verilog_seg7/db
verilog_seg7
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