文件名称:an488_design_example
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经典基于FPGA的LCD显示器的控制模块-FPGA-based LCD display control module
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下载文件列表
an488_design_example/code/
an488_design_example/code/stepmot.v
an488_design_example/modelsim/
an488_design_example/modelsim/stepmot.v
an488_design_example/modelsim/stepmot_sim.cr.mti
an488_design_example/modelsim/stepmot_sim.mpf
an488_design_example/modelsim/test_stepmot.v
an488_design_example/modelsim/transcript
an488_design_example/modelsim/wave.bmp
an488_design_example/modelsim/wave.do
an488_design_example/modelsim/work/
an488_design_example/modelsim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/
an488_design_example/modelsim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/verilog.psm
an488_design_example/modelsim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/_primary.dat
an488_design_example/modelsim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/_primary.vhd
an488_design_example/modelsim/work/divider/
an488_design_example/modelsim/work/divider/verilog.psm
an488_design_example/modelsim/work/divider/_primary.dat
an488_design_example/modelsim/work/divider/_primary.vhd
an488_design_example/modelsim/work/divider1/
an488_design_example/modelsim/work/divider1/verilog.psm
an488_design_example/modelsim/work/divider1/_primary.dat
an488_design_example/modelsim/work/divider1/_primary.vhd
an488_design_example/modelsim/work/maxii_and1/
an488_design_example/modelsim/work/maxii_and1/verilog.psm
an488_design_example/modelsim/work/maxii_and1/_primary.dat
an488_design_example/modelsim/work/maxii_and1/_primary.vhd
an488_design_example/modelsim/work/maxii_and16/
an488_design_example/modelsim/work/maxii_and16/verilog.psm
an488_design_example/modelsim/work/maxii_and16/_primary.dat
an488_design_example/modelsim/work/maxii_and16/_primary.vhd
an488_design_example/modelsim/work/maxii_asynch_lcell/
an488_design_example/modelsim/work/maxii_asynch_lcell/verilog.psm
an488_design_example/modelsim/work/maxii_asynch_lcell/_primary.dat
an488_design_example/modelsim/work/maxii_asynch_lcell/_primary.vhd
an488_design_example/modelsim/work/maxii_b17mux21/
an488_design_example/modelsim/work/maxii_b17mux21/verilog.psm
an488_design_example/modelsim/work/maxii_b17mux21/_primary.dat
an488_design_example/modelsim/work/maxii_b17mux21/_primary.vhd
an488_design_example/modelsim/work/maxii_b5mux21/
an488_design_example/modelsim/work/maxii_b5mux21/verilog.psm
an488_design_example/modelsim/work/maxii_b5mux21/_primary.dat
an488_design_example/modelsim/work/maxii_b5mux21/_primary.vhd
an488_design_example/modelsim/work/maxii_bmux21/
an488_design_example/modelsim/work/maxii_bmux21/verilog.psm
an488_design_example/modelsim/work/maxii_bmux21/_primary.dat
an488_design_example/modelsim/work/maxii_bmux21/_primary.vhd
an488_design_example/modelsim/work/maxii_crcblock/
an488_design_example/modelsim/work/maxii_crcblock/verilog.psm
an488_design_example/modelsim/work/maxii_crcblock/_primary.dat
an488_design_example/modelsim/work/maxii_crcblock/_primary.vhd
an488_design_example/modelsim/work/maxii_dffe/
an488_design_example/modelsim/work/maxii_dffe/verilog.psm
an488_design_example/modelsim/work/maxii_dffe/_primary.dat
an488_design_example/modelsim/work/maxii_dffe/_primary.vhd
an488_design_example/modelsim/work/maxii_io/
an488_design_example/modelsim/work/maxii_io/verilog.psm
an488_design_example/modelsim/work/maxii_io/_primary.dat
an488_design_example/modelsim/work/maxii_io/_primary.vhd
an488_design_example/modelsim/work/maxii_jtag/
an488_design_example/modelsim/work/maxii_jtag/verilog.psm
an488_design_example/modelsim/work/maxii_jtag/_primary.dat
an488_design_example/modelsim/work/maxii_jtag/_primary.vhd
an488_design_example/modelsim/work/maxii_latch/
an488_design_example/modelsim/work/maxii_latch/verilog.psm
an488_design_example/modelsim/work/maxii_latch/_primary.dat
an488_design_example/modelsim/work/maxii_latch/_primary.vhd
an488_design_example/modelsim/work/maxii_lcell/
an488_design_example/modelsim/work/maxii_lcell/verilog.psm
an488_design_example/modelsim/work/maxii_lcell/_primary.dat
an488_design_example/modelsim/work/maxii_lcell/_primary.vhd
an488_design_example/modelsim/work/maxii_lcell_register/
an488_design_example/modelsim/work/maxii_lcell_register/verilog.psm
an488_design_example/modelsim/work/maxii_lcell_register/_primary.dat
an488_design_example/modelsim/work/maxii_lcell_register/_primary.vhd
an488_design_example/modelsim/work/maxii_mux21/
an488_design_example/modelsim/work/maxii_mux21/verilog.psm
an488_design_example/modelsim/work/maxii_mux21/_primary.dat
an488_design_example/modelsim/work/maxii_mux21/_primary.vhd
an488_design_example/modelsim/work/maxii_mux41/
an488_design_example/modelsim/work/maxii_mux41/verilog.psm
an488_design_example/modelsim/work/maxii_mux41/_primary.dat
an488_design_example/modelsim/work/maxii_mux41/_primary.vhd
an488_design_example/modelsim/work/maxii_nmux21/
an488_design_example/modelsim/work/maxii_nmux21/verilog.psm
an488_design_example/modelsim/work/maxii_nmux21/_primary.dat
an488_design_example/modelsim/work/maxii_nmux21/_primary.vhd
an488_design_example/modelsim/work/maxii_routing_wire/
an488_design_example/modelsim/work/maxii_routing_wire/verilog.psm
an488_design_example/modelsim/work/maxii_routing_wire/_primary.dat
an488_design_example/modelsim/work/maxii_routing_wire/_primary.vhd
an48
an488_design_example/code/stepmot.v
an488_design_example/modelsim/
an488_design_example/modelsim/stepmot.v
an488_design_example/modelsim/stepmot_sim.cr.mti
an488_design_example/modelsim/stepmot_sim.mpf
an488_design_example/modelsim/test_stepmot.v
an488_design_example/modelsim/transcript
an488_design_example/modelsim/wave.bmp
an488_design_example/modelsim/wave.do
an488_design_example/modelsim/work/
an488_design_example/modelsim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/
an488_design_example/modelsim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/verilog.psm
an488_design_example/modelsim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/_primary.dat
an488_design_example/modelsim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/_primary.vhd
an488_design_example/modelsim/work/divider/
an488_design_example/modelsim/work/divider/verilog.psm
an488_design_example/modelsim/work/divider/_primary.dat
an488_design_example/modelsim/work/divider/_primary.vhd
an488_design_example/modelsim/work/divider1/
an488_design_example/modelsim/work/divider1/verilog.psm
an488_design_example/modelsim/work/divider1/_primary.dat
an488_design_example/modelsim/work/divider1/_primary.vhd
an488_design_example/modelsim/work/maxii_and1/
an488_design_example/modelsim/work/maxii_and1/verilog.psm
an488_design_example/modelsim/work/maxii_and1/_primary.dat
an488_design_example/modelsim/work/maxii_and1/_primary.vhd
an488_design_example/modelsim/work/maxii_and16/
an488_design_example/modelsim/work/maxii_and16/verilog.psm
an488_design_example/modelsim/work/maxii_and16/_primary.dat
an488_design_example/modelsim/work/maxii_and16/_primary.vhd
an488_design_example/modelsim/work/maxii_asynch_lcell/
an488_design_example/modelsim/work/maxii_asynch_lcell/verilog.psm
an488_design_example/modelsim/work/maxii_asynch_lcell/_primary.dat
an488_design_example/modelsim/work/maxii_asynch_lcell/_primary.vhd
an488_design_example/modelsim/work/maxii_b17mux21/
an488_design_example/modelsim/work/maxii_b17mux21/verilog.psm
an488_design_example/modelsim/work/maxii_b17mux21/_primary.dat
an488_design_example/modelsim/work/maxii_b17mux21/_primary.vhd
an488_design_example/modelsim/work/maxii_b5mux21/
an488_design_example/modelsim/work/maxii_b5mux21/verilog.psm
an488_design_example/modelsim/work/maxii_b5mux21/_primary.dat
an488_design_example/modelsim/work/maxii_b5mux21/_primary.vhd
an488_design_example/modelsim/work/maxii_bmux21/
an488_design_example/modelsim/work/maxii_bmux21/verilog.psm
an488_design_example/modelsim/work/maxii_bmux21/_primary.dat
an488_design_example/modelsim/work/maxii_bmux21/_primary.vhd
an488_design_example/modelsim/work/maxii_crcblock/
an488_design_example/modelsim/work/maxii_crcblock/verilog.psm
an488_design_example/modelsim/work/maxii_crcblock/_primary.dat
an488_design_example/modelsim/work/maxii_crcblock/_primary.vhd
an488_design_example/modelsim/work/maxii_dffe/
an488_design_example/modelsim/work/maxii_dffe/verilog.psm
an488_design_example/modelsim/work/maxii_dffe/_primary.dat
an488_design_example/modelsim/work/maxii_dffe/_primary.vhd
an488_design_example/modelsim/work/maxii_io/
an488_design_example/modelsim/work/maxii_io/verilog.psm
an488_design_example/modelsim/work/maxii_io/_primary.dat
an488_design_example/modelsim/work/maxii_io/_primary.vhd
an488_design_example/modelsim/work/maxii_jtag/
an488_design_example/modelsim/work/maxii_jtag/verilog.psm
an488_design_example/modelsim/work/maxii_jtag/_primary.dat
an488_design_example/modelsim/work/maxii_jtag/_primary.vhd
an488_design_example/modelsim/work/maxii_latch/
an488_design_example/modelsim/work/maxii_latch/verilog.psm
an488_design_example/modelsim/work/maxii_latch/_primary.dat
an488_design_example/modelsim/work/maxii_latch/_primary.vhd
an488_design_example/modelsim/work/maxii_lcell/
an488_design_example/modelsim/work/maxii_lcell/verilog.psm
an488_design_example/modelsim/work/maxii_lcell/_primary.dat
an488_design_example/modelsim/work/maxii_lcell/_primary.vhd
an488_design_example/modelsim/work/maxii_lcell_register/
an488_design_example/modelsim/work/maxii_lcell_register/verilog.psm
an488_design_example/modelsim/work/maxii_lcell_register/_primary.dat
an488_design_example/modelsim/work/maxii_lcell_register/_primary.vhd
an488_design_example/modelsim/work/maxii_mux21/
an488_design_example/modelsim/work/maxii_mux21/verilog.psm
an488_design_example/modelsim/work/maxii_mux21/_primary.dat
an488_design_example/modelsim/work/maxii_mux21/_primary.vhd
an488_design_example/modelsim/work/maxii_mux41/
an488_design_example/modelsim/work/maxii_mux41/verilog.psm
an488_design_example/modelsim/work/maxii_mux41/_primary.dat
an488_design_example/modelsim/work/maxii_mux41/_primary.vhd
an488_design_example/modelsim/work/maxii_nmux21/
an488_design_example/modelsim/work/maxii_nmux21/verilog.psm
an488_design_example/modelsim/work/maxii_nmux21/_primary.dat
an488_design_example/modelsim/work/maxii_nmux21/_primary.vhd
an488_design_example/modelsim/work/maxii_routing_wire/
an488_design_example/modelsim/work/maxii_routing_wire/verilog.psm
an488_design_example/modelsim/work/maxii_routing_wire/_primary.dat
an488_design_example/modelsim/work/maxii_routing_wire/_primary.vhd
an48
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