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文件名称:imdct_dsp

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  • 上传时间:
    2012-11-16
  • 文件大小:
    6.84mb
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AAC的idmct模块, 没有找到verilog开发环境,但是本模块是用verilog编写的。-AAC' s idmct module, did not find verilog development environment, but this module is written in verilog.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

imdct_dsp/
imdct_dsp/Blank512.hex
imdct_dsp/bu.v
imdct_dsp/cu.v
imdct_dsp/finish_pulse.v
imdct_dsp/flag.v
imdct_dsp/hard_imag64.txt
imdct_dsp/imdct.cr.mti
imdct_dsp/imdct.mpf
imdct_dsp/imdct.v
imdct_dsp/imdct.v.bak
imdct_dsp/imdct_bench.v
imdct_dsp/imdct_bench.v.bak
imdct_dsp/imdct_bench_tester.v
imdct_dsp/imdct_dsp.v
imdct_dsp/mu.v
imdct_dsp/mux21.v
imdct_dsp/mux21IR.v
imdct_dsp/mux21IR.v.bak
imdct_dsp/mux41.v
imdct_dsp/OriSpecRom1024.hex
imdct_dsp/OriSpecRom1024.qip
imdct_dsp/OriSpecRom1024.v
imdct_dsp/OriSpecRom1024.ver
imdct_dsp/readme.txt
imdct_dsp/send_spec.v
imdct_dsp/SopRom512.hex
imdct_dsp/SopRom512.qip
imdct_dsp/SopRom512.v
imdct_dsp/SopRom512.ver
imdct_dsp/SopRom64.hex
imdct_dsp/SopRom64.qip
imdct_dsp/SopRom64.v
imdct_dsp/SopRom64.ver
imdct_dsp/sram512.v
imdct_dsp/TfRom256.hex
imdct_dsp/TfRom256.qip
imdct_dsp/TfRom256.v
imdct_dsp/TfRom256.ver
imdct_dsp/TfRom32.hex
imdct_dsp/TfRom32.qip
imdct_dsp/TfRom32.v
imdct_dsp/TfRom32.ver
imdct_dsp/transcript
imdct_dsp/vish_stacktrace.vstf
imdct_dsp/vsim.wlf
imdct_dsp/work/
imdct_dsp/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/
imdct_dsp/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
imdct_dsp/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
imdct_dsp/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
imdct_dsp/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/
imdct_dsp/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/verilog.asm
imdct_dsp/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
imdct_dsp/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
imdct_dsp/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/
imdct_dsp/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/verilog.asm
imdct_dsp/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat
imdct_dsp/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd
imdct_dsp/work/@m@f_cycloneiii_pll/
imdct_dsp/work/@m@f_cycloneiii_pll/verilog.asm
imdct_dsp/work/@m@f_cycloneiii_pll/_primary.dat
imdct_dsp/work/@m@f_cycloneiii_pll/_primary.vhd
imdct_dsp/work/@m@f_pll_reg/
imdct_dsp/work/@m@f_pll_reg/verilog.asm
imdct_dsp/work/@m@f_pll_reg/_primary.dat
imdct_dsp/work/@m@f_pll_reg/_primary.vhd
imdct_dsp/work/@m@f_stratixiii_pll/
imdct_dsp/work/@m@f_stratixiii_pll/verilog.asm
imdct_dsp/work/@m@f_stratixiii_pll/_primary.dat
imdct_dsp/work/@m@f_stratixiii_pll/_primary.vhd
imdct_dsp/work/@m@f_stratixii_pll/
imdct_dsp/work/@m@f_stratixii_pll/verilog.asm
imdct_dsp/work/@m@f_stratixii_pll/_primary.dat
imdct_dsp/work/@m@f_stratixii_pll/_primary.vhd
imdct_dsp/work/@m@f_stratix_pll/
imdct_dsp/work/@m@f_stratix_pll/verilog.asm
imdct_dsp/work/@m@f_stratix_pll/_primary.dat
imdct_dsp/work/@m@f_stratix_pll/_primary.vhd
imdct_dsp/work/@ori@spec@rom1024/
imdct_dsp/work/@ori@spec@rom1024/verilog.asm
imdct_dsp/work/@ori@spec@rom1024/_primary.dat
imdct_dsp/work/@ori@spec@rom1024/_primary.vhd
imdct_dsp/work/@sop@rom512/
imdct_dsp/work/@sop@rom512/verilog.asm
imdct_dsp/work/@sop@rom512/_primary.dat
imdct_dsp/work/@sop@rom512/_primary.vhd
imdct_dsp/work/@sop@rom512_tester/
imdct_dsp/work/@sop@rom512_tester/verilog.asm
imdct_dsp/work/@sop@rom512_tester/_primary.dat
imdct_dsp/work/@sop@rom512_tester/_primary.vhd
imdct_dsp/work/@sop@rom64/
imdct_dsp/work/@sop@rom64/verilog.asm
imdct_dsp/work/@sop@rom64/_primary.dat
imdct_dsp/work/@sop@rom64/_primary.vhd
imdct_dsp/work/@tf@rom256/
imdct_dsp/work/@tf@rom256/verilog.asm
imdct_dsp/work/@tf@rom256/_primary.dat
imdct_dsp/work/@tf@rom256/_primary.vhd
imdct_dsp/work/@tf@rom32/
imdct_dsp/work/@tf@rom32/verilog.asm
imdct_dsp/work/@tf@rom32/_primary.dat
imdct_dsp/work/@tf@rom32/_primary.vhd
imdct_dsp/work/alt3pram/
imdct_dsp/work/alt3pram/verilog.asm
imdct_dsp/work/alt3pram/_primary.dat
imdct_dsp/work/alt3pram/_primary.vhd
imdct_dsp/work/altaccumulate/
imdct_dsp/work/altaccumulate/verilog.asm
imdct_dsp/work/altaccumulate/_primary.dat
imdct_dsp/work/altaccumulate/_primary.vhd
imdct_dsp/work/altcam/
imdct_dsp/work/altcam/verilog.asm
imdct_dsp/work/altcam/_primary.dat
imdct_dsp/work/altcam/_primary.vhd
imdct_dsp/work/altclklock/
imdct_dsp/work/altclklock/verilog.asm
imdct_dsp/work/altclklock/_primary.dat
imdct_dsp/work/altclklock/_primary.vhd
imdct_dsp/work/altddio_bidir/
imdct_dsp/work/altddio_bidir/verilog.asm
imdct_dsp/work/altddio_bidir/_primary.dat
imdct_dsp/work/altddio_bidir/_primary.vhd
imdct_dsp/work/altddio_in/
imdct_dsp/work/altddio_in/verilog.asm
imdct_dsp/work/altddio_in/_primary.dat
imdct_dsp/work/altddio_in/_primary.vhd
imdct_dsp/work/altddio_out/
imdct_dsp/work/altddio_out/verilog.asm
imdct_dsp/work/altddio_out/_primary.dat
imdct_dsp/work/altddio_out/_primary.vhd
imdct_dsp/work/altdpram/
imdct_dsp/work/altdpram/verilog.asm
imdct_dsp/work/altdpram/_primary.dat
imdct_dsp/work/altdpram/_primary.vhd
imdct_dsp/work/altfp_mult/
imdct_dsp/work/altfp_mult/verilog.asm
imdct_dsp/work/altfp_mult/_primary.dat
imdct_dsp/work/altfp_mult/_primary.vhd
imdct_dsp/work/altlvds_rx/
imdct_dsp/work/altlvds_rx/verilog.asm
imdct_dsp/work/altlvds_rx/_primary.dat
imdct_dsp/work/altlvds_r

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