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文件名称:ethernet_tri_mode_latest.tar

  • 所属分类：
    Other systems
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    3.05mb
  • 已下载：
    0次
  • 提 供 者：
    G*****
  • 相关连接：
    无
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10_100 0 Mbps tri-mode ethernet MAC implements a MAC controller

conforming to IEEE 802.3 specification. It is designed to use less than 2000

LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce

technology dependance.To increase the flexibility,three optional modules can be

added to or removed from the project.

A GUI configuration interface,created by tcl/tk scr ipt language,is

convenient for configuring optional modules,FiFo depth and verifcation

parameters. Furthermore,a verifcation system was designed with tcl/tk user

interface,by which the stimulus can be generated automatically and the output

packets can be verified with CRC-32 checksum.-10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller

conforming to IEEE 802.3 specification. It is designed to use less than 2000

LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce

technology dependance.To increase the flexibility,three optional modules can be

added to or removed from the project.

A GUI configuration interface,created by tcl/tk scr ipt language,is

convenient for configuring optional modules,FiFo depth and verifcation

parameters. Furthermore,a verifcation system was designed with tcl/tk user

interface,by which the stimulus can be generated automatically and the output

packets can be verified with CRC-32 checksum.
相关搜索： Ethernet MAC ethernet_tri_mo Tri Mode

(系统自动生成,下载前可以参看下载内容)

下载文件列表

./
./ethernet_tri_mode/
./ethernet_tri_mode/tags/
./ethernet_tri_mode/tags/arelease/
./ethernet_tri_mode/tags/arelease/doc/
./ethernet_tri_mode/tags/arelease/doc/RGMII_DataSheet.pdf
./ethernet_tri_mode/tags/rel-1-0/
./ethernet_tri_mode/tags/rel-1-0/bench/
./ethernet_tri_mode/tags/rel-1-0/bench/verilog/
./ethernet_tri_mode/tags/rel-1-0/bench/verilog/reg_int_sim.v
./ethernet_tri_mode/tags/rel-1-0/bench/verilog/host_sim.v
./ethernet_tri_mode/tags/rel-1-0/bench/verilog/User_int_sim.v
./ethernet_tri_mode/tags/rel-1-0/bench/verilog/tb_top.v
./ethernet_tri_mode/tags/rel-1-0/bench/verilog/altera_mf.v
./ethernet_tri_mode/tags/rel-1-0/bench/verilog/Phy_sim.v
./ethernet_tri_mode/tags/rel-1-0/start.tcl
./ethernet_tri_mode/tags/rel-1-0/doc/
./ethernet_tri_mode/tags/rel-1-0/doc/Tri-mode_Ethernet_MAC_Verification_plan.pdf
./ethernet_tri_mode/tags/rel-1-0/doc/Tri-mode_Ethernet_MAC_Specifications.pdf
./ethernet_tri_mode/tags/rel-1-0/rtl/
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/reg_int.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/TECH/
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/TECH/CLK_SWITCH.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/TECH/CLK_DIV2.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/TECH/duram.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/RMON.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/Phy_int.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_rx/
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_rx/MAC_rx_add_chk.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_rx/MAC_rx_ctrl.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_rx/CRC_chk.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_rx/Broadcast_filter.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_rx/MAC_rx_FF.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_tx/
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_tx/MAC_tx_addr_add.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_tx/CRC_gen.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_tx/MAC_tx_FF.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_tx/flow_ctrl.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_tx/Ramdon_gen.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/header.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_rx.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/miim/
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/miim/eth_outputcontrol.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/miim/timescale.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/miim/eth_shiftreg.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/miim/eth_clockgen.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_top.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/eth_miim.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/MAC_tx.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/RMON/
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/RMON/RMON_ctrl.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/RMON/RMON_dpram.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/RMON/RMON_addr_gen.v
./ethernet_tri_mode/tags/rel-1-0/rtl/verilog/Clk_ctrl.v
./ethernet_tri_mode/tags/rel-1-0/sim/
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/log/
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/log/ncsim.log
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/script/
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/script/run_proc.tcl
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/script/filesel.tcl
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/script/start_verify.tcl
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/script/user_lib.tcl
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/script/batch_mode.tcl
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/script/run.tcl
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/script/set_reg_data.tcl
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/script/set_stimulus.tcl
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/data/
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/data/10Mbps_duplex.vec
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/data/CPU.vec
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/data/target_mac_check.vec
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/data/46-50.ini
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/data/batch.dat
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/data/1000Mbps_duplex.vec
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/data/source_mac_replace.vec
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/data/flow_ctrl.vec
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/data/100Mbps_duplex.vec
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/data/config.ini
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/bin/
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/bin/sim_only.nc
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll
./ethernet_tri_mode/tags/rel-1-0/sim/rtl_sim/ncsim_sim/bin/ip_32W

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