SoC中CPU总线一般采用应答机制，是非实时的，数据的处理采用中断响应机制以发挥效率。处理特定实时数据并没有固定的延时与稳定的吞吐率，因此需要设计一个模块来处理实时数据到非实时总线之间的平滑过度问题。作者以此模块设计为例，阐述非实时总线中实时数据切换的设计理念与几个实用技术。-SoC, CPU buses generally use response mechanism, non-real-time, data processing using interrupt response mechanism to achieve efficiency. Deal with specific real-time data, and there is no fixed time delay and stability in throughput, so need to design a module to handle real-time data to a non-real-time smoothing over the issue between the bus. By this modular design as an example to explain the non-real-time real-time data bus switch design concepts with several practical technology.