The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce

race conditions between verification code and SystemVerilog designs. The new regions also

facilitate race-free Assertion Based Verification (ABV).

This paper details common Verilog verification strategies and how the new event regions

facilitate construction of race-free testbenches using new SystemVerilog capabilities. An in-

depth explanation of SystemVerilog event regions is included to help understand how race-

reduction goals have been met. Important design & testbench coding guidelines are also

included.-The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce

race conditions between verification code and SystemVerilog designs. The new regions also

facilitate race-free Assertion Based Verification (ABV).

This paper details common Verilog verification strategies and how the new event regions

facilitate construction of race-free testbenches using new SystemVerilog capabilities. An in-

depth explanation of SystemVerilog event regions is included to help understand how race-

reduction goals have been met. Important　design & testbench coding guidelines are also

included.