文件名称:lab4
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经典嵌入式EDK设计教程,使用的是XILINX公司的EDK开发软件。这是教程的第四部分-Classic embedded EDK design tutorials, using XILINX' s EDK software development. This is the fourth part of the tutorial
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下载文件列表
lab4/system.bmm
lab4/system.make
lab4/system.mhs
lab4/system.mss
lab4/system.mvs
lab4/system.xmp
lab4/xps.cmd
lab4/myip/jtagppc_cntlr_v1_00_a/hdl/vhdl/jtagppc_cntlr.vhd
lab4/myip/jtagppc_cntlr_v1_00_a/hdl/verilog/jtagppc_cntlr.v
lab4/myip/jtagppc_cntlr_v1_00_a/data/jtagppc_cntlr_v2_0_0.mpd
lab4/myip/jtagppc_cntlr_v1_00_a/data/jtagppc_cntlr_v2_0_0.pao
lab4/myip/ddr_clock_module_ref_v1_00_a/hdl/vhdl/ddr_clock_module_ref.vhd
lab4/myip/ddr_clock_module_ref_v1_00_a/data/ddr_clock_module_ref_v2_0_0.mpd
lab4/myip/ddr_clock_module_ref_v1_00_a/data/ddr_clock_module_ref_v2_0_0.pao
lab4/myip/dcm_ip/hdl/vhdl/dcm_ip.vhd
lab4/myip/dcm_ip/data/dcm_ip_v2_0_0.mpd
lab4/myip/dcm_ip/data/dcm_ip_v2_0_0.pao
lab4/myip/bram_block_v1_00_a/hdl/vhdl/bram1_elaborate.vhd
lab4/etc/bitgen.opt
lab4/etc/bitgen.ut
lab4/etc/download.cmd
lab4/etc/fast_runtime.opt
lab4/etc/system.mss
lab4/etc/xc18v04_vq44.bsd
lab4/etc/xccace.bsd
lab4/etc/_impact.cmd
lab4/data/libgen.opt
lab4/data/platgen.opt
lab4/data/simgen.opt
lab4/data/system.make
lab4/data/system.mhs
lab4/data/system.mss
lab4/data/system.ucf
lab4/data/xpsxflow.opt
lab4/data/ppc405_i/lib/compiler.opt
lab4/code/hello.c
lab4/code/linker_script
lab4/code/mem_test.c
lab4/code/mem_test2.c
lab4/code/web.c
lab4/code/web.h
lab4/myip/jtagppc_cntlr_v1_00_a/hdl/vhdl
lab4/myip/jtagppc_cntlr_v1_00_a/hdl/verilog
lab4/myip/ddr_clock_module_ref_v1_00_a/hdl/vhdl
lab4/myip/dcm_ip/hdl/vhdl
lab4/myip/bram_block_v1_00_a/hdl/vhdl
lab4/myip/jtagppc_cntlr_v1_00_a/hdl
lab4/myip/jtagppc_cntlr_v1_00_a/data
lab4/myip/ddr_clock_module_ref_v1_00_a/hdl
lab4/myip/ddr_clock_module_ref_v1_00_a/data
lab4/myip/dcm_ip/hdl
lab4/myip/dcm_ip/data
lab4/myip/bram_block_v1_00_a/hdl
lab4/data/ppc405_i/lib
lab4/myip/jtagppc_cntlr_v1_00_a
lab4/myip/ddr_clock_module_ref_v1_00_a
lab4/myip/dcm_ip
lab4/myip/bram_block_v1_00_a
lab4/data/ppc405_i
lab4/myip
lab4/etc
lab4/data
lab4/code
lab4
lab4/system.make
lab4/system.mhs
lab4/system.mss
lab4/system.mvs
lab4/system.xmp
lab4/xps.cmd
lab4/myip/jtagppc_cntlr_v1_00_a/hdl/vhdl/jtagppc_cntlr.vhd
lab4/myip/jtagppc_cntlr_v1_00_a/hdl/verilog/jtagppc_cntlr.v
lab4/myip/jtagppc_cntlr_v1_00_a/data/jtagppc_cntlr_v2_0_0.mpd
lab4/myip/jtagppc_cntlr_v1_00_a/data/jtagppc_cntlr_v2_0_0.pao
lab4/myip/ddr_clock_module_ref_v1_00_a/hdl/vhdl/ddr_clock_module_ref.vhd
lab4/myip/ddr_clock_module_ref_v1_00_a/data/ddr_clock_module_ref_v2_0_0.mpd
lab4/myip/ddr_clock_module_ref_v1_00_a/data/ddr_clock_module_ref_v2_0_0.pao
lab4/myip/dcm_ip/hdl/vhdl/dcm_ip.vhd
lab4/myip/dcm_ip/data/dcm_ip_v2_0_0.mpd
lab4/myip/dcm_ip/data/dcm_ip_v2_0_0.pao
lab4/myip/bram_block_v1_00_a/hdl/vhdl/bram1_elaborate.vhd
lab4/etc/bitgen.opt
lab4/etc/bitgen.ut
lab4/etc/download.cmd
lab4/etc/fast_runtime.opt
lab4/etc/system.mss
lab4/etc/xc18v04_vq44.bsd
lab4/etc/xccace.bsd
lab4/etc/_impact.cmd
lab4/data/libgen.opt
lab4/data/platgen.opt
lab4/data/simgen.opt
lab4/data/system.make
lab4/data/system.mhs
lab4/data/system.mss
lab4/data/system.ucf
lab4/data/xpsxflow.opt
lab4/data/ppc405_i/lib/compiler.opt
lab4/code/hello.c
lab4/code/linker_script
lab4/code/mem_test.c
lab4/code/mem_test2.c
lab4/code/web.c
lab4/code/web.h
lab4/myip/jtagppc_cntlr_v1_00_a/hdl/vhdl
lab4/myip/jtagppc_cntlr_v1_00_a/hdl/verilog
lab4/myip/ddr_clock_module_ref_v1_00_a/hdl/vhdl
lab4/myip/dcm_ip/hdl/vhdl
lab4/myip/bram_block_v1_00_a/hdl/vhdl
lab4/myip/jtagppc_cntlr_v1_00_a/hdl
lab4/myip/jtagppc_cntlr_v1_00_a/data
lab4/myip/ddr_clock_module_ref_v1_00_a/hdl
lab4/myip/ddr_clock_module_ref_v1_00_a/data
lab4/myip/dcm_ip/hdl
lab4/myip/dcm_ip/data
lab4/myip/bram_block_v1_00_a/hdl
lab4/data/ppc405_i/lib
lab4/myip/jtagppc_cntlr_v1_00_a
lab4/myip/ddr_clock_module_ref_v1_00_a
lab4/myip/dcm_ip
lab4/myip/bram_block_v1_00_a
lab4/data/ppc405_i
lab4/myip
lab4/etc
lab4/data
lab4/code
lab4
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