文件名称:ddrct_gen_o4_1_008_1
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ddrct_gen_o4_1_008/orca4/
ddrct_gen_o4_1_008/orca4/ver1/
ddrct_gen_o4_1_008/orca4/ver1/eval/
ddrct_gen_o4_1_008/orca4/ver1/eval/simulation/
ddrct_gen_o4_1_008/orca4/ver1/eval/simulation/scripts/
ddrct_gen_o4_1_008/orca4/ver1/eval/simulation/scripts/run_sim_ddrgen.do
ddrct_gen_o4_1_008/orca4/ver1/eval/testbench/
ddrct_gen_o4_1_008/orca4/ver1/eval/testbench/ddr_pll_orca_sim.v
ddrct_gen_o4_1_008/orca4/ver1/eval/testbench/ddr_top_tb.v
ddrct_gen_o4_1_008/orca4/ver1/eval/tests/
ddrct_gen_o4_1_008/orca4/ver1/eval/tests/stimuli_basicrw_cmd.v
ddrct_gen_o4_1_008/orca4/ver1/gui_script/
ddrct_gen_o4_1_008/orca4/ver1/lib/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@b@m@z12/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@b@m@z12/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@b@m@z12/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@b@m@z12/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@d@c@e32@x4/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@d@c@e32@x4/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@d@c@e32@x4/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@d@c@e32@x4/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@f@d1@p3@d@x/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@f@d1@p3@d@x/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@f@d1@p3@d@x/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@f@d1@p3@d@x/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@h@p@p@l@l/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@h@p@p@l@l/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@h@p@p@l@l/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@h@p@p@l@l/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@s@y@n3@r@a@m/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@s@y@n3@r@a@m/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@s@y@n3@r@a@m/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@s@y@n3@r@a@m/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@u@d@f@d@l5_@u@d@p_@x/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@u@d@f@d@l5_@u@d@p_@x/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@u@d@f@d@l5_@u@d@p_@x/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@u@d@f@d@l5_@u@d@p_@x/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@h@i/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@h@i/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@h@i/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@h@i/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@l@o/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@l@o/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@l@o/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@l@o/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddrct_gen_o4_1_008/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddrct_gen_o4_1_008/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddrct_gen_o4_1_008/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddrct_gen_o4_1_008/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_cmd_exe/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_cmd_exe/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_cmd_exe/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_cmd_exe/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_databusif/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_databusif/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_databusif/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_databusif/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_genericif/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_genericif/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_genericif/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_genericif/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_initctrl/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_initctrl/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_initctrl/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_initctrl/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_msm/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_msm/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_msm/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_msm/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_sm/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_sm/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_sm/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_sm/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/mt46v16m8/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/mt46v16m8/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/mt46v16m8/_primary.dat
ddrct_gen_o4_1_00
ddrct_gen_o4_1_008/orca4/ver1/
ddrct_gen_o4_1_008/orca4/ver1/eval/
ddrct_gen_o4_1_008/orca4/ver1/eval/simulation/
ddrct_gen_o4_1_008/orca4/ver1/eval/simulation/scripts/
ddrct_gen_o4_1_008/orca4/ver1/eval/simulation/scripts/run_sim_ddrgen.do
ddrct_gen_o4_1_008/orca4/ver1/eval/testbench/
ddrct_gen_o4_1_008/orca4/ver1/eval/testbench/ddr_pll_orca_sim.v
ddrct_gen_o4_1_008/orca4/ver1/eval/testbench/ddr_top_tb.v
ddrct_gen_o4_1_008/orca4/ver1/eval/tests/
ddrct_gen_o4_1_008/orca4/ver1/eval/tests/stimuli_basicrw_cmd.v
ddrct_gen_o4_1_008/orca4/ver1/gui_script/
ddrct_gen_o4_1_008/orca4/ver1/lib/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@b@m@z12/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@b@m@z12/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@b@m@z12/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@b@m@z12/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@d@c@e32@x4/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@d@c@e32@x4/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@d@c@e32@x4/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@d@c@e32@x4/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@f@d1@p3@d@x/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@f@d1@p3@d@x/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@f@d1@p3@d@x/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@f@d1@p3@d@x/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@h@p@p@l@l/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@h@p@p@l@l/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@h@p@p@l@l/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@h@p@p@l@l/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@s@y@n3@r@a@m/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@s@y@n3@r@a@m/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@s@y@n3@r@a@m/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@s@y@n3@r@a@m/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@u@d@f@d@l5_@u@d@p_@x/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@u@d@f@d@l5_@u@d@p_@x/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@u@d@f@d@l5_@u@d@p_@x/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@u@d@f@d@l5_@u@d@p_@x/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@h@i/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@h@i/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@h@i/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@h@i/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@l@o/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@l@o/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@l@o/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/@v@l@o/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddrct_gen_o4_1_008/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddrct_gen_o4_1_008/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddrct_gen_o4_1_008/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddrct_gen_o4_1_008/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_cmd_exe/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_cmd_exe/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_cmd_exe/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_cmd_exe/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_databusif/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_databusif/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_databusif/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_databusif/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_genericif/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_genericif/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_genericif/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_genericif/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_initctrl/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_initctrl/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_initctrl/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_initctrl/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_msm/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_msm/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_msm/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_msm/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_sm/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_sm/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_sm/_primary.dat
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/ddr_sm/_primary.vhd
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/mt46v16m8/
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/mt46v16m8/verilog.asm
ddrct_gen_o4_1_008/orca4/ver1/lib/modelsim/work/mt46v16m8/_primary.dat
ddrct_gen_o4_1_00
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