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文件名称:doc17414x90

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    631.24kb
  • 已下载：
    0次
  • 提 供 者：
    张***
  • 相关连接：
    无
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ddr设计控制器，源代码！Verilog代码！-设计控制器，源代码！Verilog代码！
相关搜索： ddr DDR verilog DDR 控制器

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下载文件列表

ddrct_gen_xm_4_001/default.css
ddrct_gen_xm_4_001/Readme.htm
ddrct_gen_xm_4_001/tutorial/
ddrct_gen_xm_4_001/xm/
ddrct_gen_xm_4_001/xm/ver4/
ddrct_gen_xm_4_001/xm/ver4/eval/
ddrct_gen_xm_4_001/xm/ver4/eval/readme.txt
ddrct_gen_xm_4_001/xm/ver4/eval/simulation/
ddrct_gen_xm_4_001/xm/ver4/eval/simulation/scripts/
ddrct_gen_xm_4_001/xm/ver4/eval/simulation/scripts/eval_ddr_sim_verilog.do
ddrct_gen_xm_4_001/xm/ver4/eval/simulation/scripts/eval_ddr_sim_vhdl.do
ddrct_gen_xm_4_001/xm/ver4/eval/testbench/
ddrct_gen_xm_4_001/xm/ver4/eval/testbench/verilog/
ddrct_gen_xm_4_001/xm/ver4/eval/testbench/verilog/test_ddr_sdram_mem_sim.v
ddrct_gen_xm_4_001/xm/ver4/eval/testbench/vhdl/
ddrct_gen_xm_4_001/xm/ver4/eval/testbench/vhdl/test_ddr_sdram_mem_sim.vhd
ddrct_gen_xm_4_001/xm/ver4/eval/tests/
ddrct_gen_xm_4_001/xm/ver4/eval/tests/stim_ddr_test_01.v
ddrct_gen_xm_4_001/xm/ver4/gui_script/
ddrct_gen_xm_4_001/xm/ver4/gui_script/module_gen.zip
ddrct_gen_xm_4_001/xm/ver4/lib/
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal/
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal/verilog.psm
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal/_primary.dat
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal/_primary.vhd
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal_cesm/
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal_cesm/verilog.psm
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal_cesm/_primary.dat
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal_cesm/_primary.vhd
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal_csm/
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal_csm/verilog.psm
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal_csm/_primary.dat
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal_csm/_primary.vhd
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal_ctsm/
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal_ctsm/verilog.psm
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal_ctsm/_primary.dat
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cal_ctsm/_primary.vhd
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cdl/
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cdl/verilog.psm
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cdl/_primary.dat
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/cdl/_primary.vhd
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/ddrct_gen_xm_4_001/
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/ddrct_gen_xm_4_001/verilog.psm
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/ddrct_gen_xm_4_001/_primary.dat
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/ddrct_gen_xm_4_001/_primary.vhd
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/init_sm/
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/init_sm/verilog.psm
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/init_sm/_primary.dat
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/init_sm/_primary.vhd
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/row_addr_tab/
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/row_addr_tab/verilog.psm
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/row_addr_tab/_primary.dat
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/row_addr_tab/_primary.vhd
ddrct_gen_xm_4_001/xm/ver4/lib/modelsim/IP_work/_info
ddrct_gen_xm_4_001/xm/ver4/par/
ddrct_gen_xm_4_001/xm/ver4/par/ddrct_gen_xm_4_001.lpc
ddrct_gen_xm_4_001/xm/ver4/par/ddrct_gen_xm_4_001.ngo
ddrct_gen_xm_4_001/xm/ver4/par/ddrct_gen_xm_4_001_synplify.prf
ddrct_gen_xm_4_001/xm/ver4/par/post_route_trace_synplify.prf
ddrct_gen_xm_4_001/xm/ver4/source/
ddrct_gen_xm_4_001/xm/ver4/source/ddr_sdram_mem_top_synp.sdc
ddrct_gen_xm_4_001/xm/ver4/source/verilog/
ddrct_gen_xm_4_001/xm/ver4/source/verilog/albuf.v
ddrct_gen_xm_4_001/xm/ver4/source/verilog/bidi_cell.v
ddrct_gen_xm_4_001/xm/ver4/source/verilog/cal_dvgen.v
ddrct_gen_xm_4_001/xm/ver4/source/verilog/ddrct_gen_xm_4_001.v
ddrct_gen_xm_4_001/xm/ver4/source/verilog/ddrct_gen_xm_4_001_params.v
ddrct_gen_xm_4_001/xm/ver4/source/verilog/ddr_data_io.v
ddrct_gen_xm_4_001/xm/ver4/source/verilog/ddr_dm_io.v
ddrct_gen_xm_4_001/xm/ver4/source/verilog/ddr_dqs_io.v
ddrct_gen_xm_4_001/xm/ver4/source/verilog/ddr_sdram_mem_top.v
ddrct_gen_xm_4_001/xm/ver4/source/verilog/dv_mod.v
ddrct_gen_xm_4_001/xm/ver4/source/verilog/kbar_clk_pll.v
ddrct_gen_xm_4_001/xm/ver4/source/verilog/pio_dvalid_gen.v
ddrct_gen_xm_4_001/xm/ver4/source/verilog/xp.v
ddrct_gen_xm_4_001/xm/ver4/source/vhdl/
ddrct_gen_xm_4_001/xm/ver4/source/vhdl/albuf.vhd
ddrct_gen_xm_4_001/xm/ver4/source/vhdl/bidi_cell.vhd
ddrct_gen_xm_4_001/xm/ver4/source/vhdl/cal_dvgen.vhd
ddrct_gen_xm_4_001/xm/ver4/source/vhdl/ddrct_gen_xm_4_001_params.vhd
ddrct_gen_xm_4_001/xm/ver4/source/vhdl/ddr_data_io.vhd
ddrct_gen_xm_4_001/xm/ver4/source/vhdl/ddr_dm_io.vhd
ddrct_gen_xm_4_001/xm/ver4/source/vhdl/ddr_dqs_io.vhd
ddrct_gen_xm_4_001/xm/ver4/source/vhdl/ddr_sdram_mem_top.vhd
ddrct_gen_xm_4_001/xm/ver4/source/vhdl/dv_mod.vhd
ddrct_gen_xm_4_001/xm/ver4/source/vhdl/kbar_clk_pll.vhd
ddrct_gen_xm_4_001/xm/ver4/source/vhdl/pio_dvalid_gen.vhd
ddrct_gen_xm_4_001/

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