文件名称:Advanced-Xilinx-FPGA
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- 上传时间：2012-11-16
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Advanced Xilinx FPGA
Design with ISE
Objectives
Describe Virtex™ -II advanced architectural features and how they can be used to
improve performance
• Create and integrate cores into your design flow using the CORE Generator™ System
• Describe the different ISE options available and how they can be used to improve
performance
• Describe a flow for obtaining timing closure with Advance Timing Constraints
• Use FloorPlanner to improve timing
• Reduce implementation time with Incremental Design Techniques and Modular Design
Techniques
• Reduce debugging time with FPGA Editor
• On-Chip Verification with ChipScope Pro-Advanced Xilinx FPGA
Design with ISE
Objectives
Describe Virtex™ -II advanced architectural features and how they can be used to
improve performance
• Create and integrate cores into your design flow using the CORE Generator™ System
• Describe the different ISE options available and how they can be used to improve
performance
• Describe a flow for obtaining timing closure with Advance Timing Constraints
• Use FloorPlanner to improve timing
• Reduce implementation time with Incremental Design Techniques and Modular Design
Techniques
• Reduce debugging time with FPGA Editor
• On-Chip Verification with ChipScope Pro
Design with ISE
Objectives
Describe Virtex™ -II advanced architectural features and how they can be used to
improve performance
• Create and integrate cores into your design flow using the CORE Generator™ System
• Describe the different ISE options available and how they can be used to improve
performance
• Describe a flow for obtaining timing closure with Advance Timing Constraints
• Use FloorPlanner to improve timing
• Reduce implementation time with Incremental Design Techniques and Modular Design
Techniques
• Reduce debugging time with FPGA Editor
• On-Chip Verification with ChipScope Pro-Advanced Xilinx FPGA
Design with ISE
Objectives
Describe Virtex™ -II advanced architectural features and how they can be used to
improve performance
• Create and integrate cores into your design flow using the CORE Generator™ System
• Describe the different ISE options available and how they can be used to improve
performance
• Describe a flow for obtaining timing closure with Advance Timing Constraints
• Use FloorPlanner to improve timing
• Reduce implementation time with Incremental Design Techniques and Modular Design
Techniques
• Reduce debugging time with FPGA Editor
• On-Chip Verification with ChipScope Pro
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