CDN加速镜像 | 设为首页 | 加入收藏夹
登陆 | 会员注册
当前位置： 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程
收藏

文件名称:T4_sdram_control

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.66mb
  • 已下载：
    0次
  • 提 供 者：
    季***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

红色飓风的EP2C20开发板的关于sdram操作的详细资料，里面有说明文档和例程分析。-Red Hurricane EP2C20 development board on the sdram details of the operation, which has made it clear documentation and routine analysis.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

T4_sdram_control/doc/read_me.doc
T4_sdram_control/doc/SDRAM.doc
T4_sdram_control/doc/sdr_sdram.pdf
T4_sdram_control/sim/altera_mf.v
T4_sdram_control/sim/Command.v
T4_sdram_control/sim/control_interface.v
T4_sdram_control/sim/mt48lc2m32b2.v
T4_sdram_control/sim/Params.v
T4_sdram_control/sim/sdram_test.cr.mti
T4_sdram_control/sim/sdram_test.mpf
T4_sdram_control/sim/sdram_test.wlf
T4_sdram_control/sim/sdram_test_tb.v
T4_sdram_control/sim/transcript
T4_sdram_control/sim/vsim.wlf
T4_sdram_control/sim/wave.do
T4_sdram_control/sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
T4_sdram_control/sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
T4_sdram_control/sim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
T4_sdram_control/sim/work/@m@f_pll_reg/verilog.asm
T4_sdram_control/sim/work/@m@f_pll_reg/_primary.dat
T4_sdram_control/sim/work/@m@f_pll_reg/_primary.vhd
T4_sdram_control/sim/work/@m@f_ram7x20_syn/verilog.asm
T4_sdram_control/sim/work/@m@f_ram7x20_syn/_primary.dat
T4_sdram_control/sim/work/@m@f_ram7x20_syn/_primary.vhd
T4_sdram_control/sim/work/@m@f_stratixii_pll/verilog.asm
T4_sdram_control/sim/work/@m@f_stratixii_pll/_primary.dat
T4_sdram_control/sim/work/@m@f_stratixii_pll/_primary.vhd
T4_sdram_control/sim/work/@m@f_stratix_pll/verilog.asm
T4_sdram_control/sim/work/@m@f_stratix_pll/_primary.dat
T4_sdram_control/sim/work/@m@f_stratix_pll/_primary.vhd
T4_sdram_control/sim/work/alt3pram/verilog.asm
T4_sdram_control/sim/work/alt3pram/_primary.dat
T4_sdram_control/sim/work/alt3pram/_primary.vhd
T4_sdram_control/sim/work/altaccumulate/verilog.asm
T4_sdram_control/sim/work/altaccumulate/_primary.dat
T4_sdram_control/sim/work/altaccumulate/_primary.vhd
T4_sdram_control/sim/work/altcam/verilog.asm
T4_sdram_control/sim/work/altcam/_primary.dat
T4_sdram_control/sim/work/altcam/_primary.vhd
T4_sdram_control/sim/work/altcdr_rx/verilog.asm
T4_sdram_control/sim/work/altcdr_rx/_primary.dat
T4_sdram_control/sim/work/altcdr_rx/_primary.vhd
T4_sdram_control/sim/work/altcdr_tx/verilog.asm
T4_sdram_control/sim/work/altcdr_tx/_primary.dat
T4_sdram_control/sim/work/altcdr_tx/_primary.vhd
T4_sdram_control/sim/work/altclklock/verilog.asm
T4_sdram_control/sim/work/altclklock/_primary.dat
T4_sdram_control/sim/work/altclklock/_primary.vhd
T4_sdram_control/sim/work/altddio_bidir/verilog.asm
T4_sdram_control/sim/work/altddio_bidir/_primary.dat
T4_sdram_control/sim/work/altddio_bidir/_primary.vhd
T4_sdram_control/sim/work/altddio_in/verilog.asm
T4_sdram_control/sim/work/altddio_in/_primary.dat
T4_sdram_control/sim/work/altddio_in/_primary.vhd
T4_sdram_control/sim/work/altddio_out/verilog.asm
T4_sdram_control/sim/work/altddio_out/_primary.dat
T4_sdram_control/sim/work/altddio_out/_primary.vhd
T4_sdram_control/sim/work/altdpram/verilog.asm
T4_sdram_control/sim/work/altdpram/_primary.dat
T4_sdram_control/sim/work/altdpram/_primary.vhd
T4_sdram_control/sim/work/altfp_mult/verilog.asm
T4_sdram_control/sim/work/altfp_mult/_primary.dat
T4_sdram_control/sim/work/altfp_mult/_primary.vhd
T4_sdram_control/sim/work/altlvds_rx/verilog.asm
T4_sdram_control/sim/work/altlvds_rx/_primary.dat
T4_sdram_control/sim/work/altlvds_rx/_primary.vhd
T4_sdram_control/sim/work/altlvds_tx/verilog.asm
T4_sdram_control/sim/work/altlvds_tx/_primary.dat
T4_sdram_control/sim/work/altlvds_tx/_primary.vhd
T4_sdram_control/sim/work/altmult_accum/verilog.asm
T4_sdram_control/sim/work/altmult_accum/_primary.dat
T4_sdram_control/sim/work/altmult_accum/_primary.vhd
T4_sdram_control/sim/work/altmult_add/verilog.asm
T4_sdram_control/sim/work/altmult_add/_primary.dat
T4_sdram_control/sim/work/altmult_add/_primary.vhd
T4_sdram_control/sim/work/altpll/verilog.asm
T4_sdram_control/sim/work/altpll/_primary.dat
T4_sdram_control/sim/work/altpll/_primary.vhd
T4_sdram_control/sim/work/altqpram/verilog.asm
T4_sdram_control/sim/work/altqpram/_primary.dat
T4_sdram_control/sim/work/altqpram/_primary.vhd
T4_sdram_control/sim/work/altshift_taps/verilog.asm
T4_sdram_control/sim/work/altshift_taps/_primary.dat
T4_sdram_control/sim/work/altshift_taps/_primary.vhd
T4_sdram_control/sim/work/altsqrt/verilog.asm
T4_sdram_control/sim/work/altsqrt/_primary.dat
T4_sdram_control/sim/work/altsqrt/_primary.vhd
T4_sdram_control/sim/work/altsyncram/verilog.asm
T4_sdram_control/sim/work/altsyncram/_primary.dat
T4_sdram_control/sim/work/altsyncram/_primary.vhd
T4_sdram_control/sim/work/alt_exc_dpram/verilog.asm
T4_sdram_control/sim/work/alt_exc_dpram/_primary.dat
T4_sdram_control/sim/work/alt_exc_dpram/_primary.vhd
T4_sdram_control/sim/work/alt_exc_upcore/verilog.asm
T4_sdram_control/sim/work/alt_exc_upcore/_primary.dat
T4_sdram_control/sim/work/alt_exc_upcore/_primary.vhd
T4_sdram_control/sim/work/arm_m_cntr/verilog.asm
T4_sdram_control/sim/work/arm_m_cntr/_primary.dat
T4_sdram_control/sim/work/arm_m_cntr/_primary.vhd
T4_sdram_control/sim/work/arm_n_cntr/verilog.asm
T4_sdram_control/sim/work/arm_n_cntr/_primary.dat
T4_sdram_control/sim/work/arm_n_cntr/_primary.vhd
T4_sdram_control/sim/work/arm_scale_cntr/verilog.asm
T4_sdram_control/sim/work/arm_scale_cntr/_primary.dat
T4_sdram_contro

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 搜珍网是交换下载平台，只提供交流渠道，下载内容来自于网络，除下载问题外，其它问题请自行百度。更多...
  • 本站已设置防盗链，请勿用迅雷、QQ旋风等下载软件下载资源，下载后用WinRAR最新版进行解压.
  • 如果您发现内容无法下载，请稍后再次尝试；或换浏览器；或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎，请到消费记录里找到下载记录反馈给我们，经确认后退回积分.
  • 如下载前有疑问，可以通过点击"提供者"的名字，查看对方的联系方式，联系对方咨询.
查看所有评论

相关评论

暂无评论内容．

发表评论

*快速评论： 推荐 一般 有密码 和说明不符 不是源码或资料 文件不全 不能解压 纯粹是垃圾
*内　　容：
*验 证 码：
搜珍网 www.dssz.com